Granted Patent B2

US 9,734,027 · App. 14/851,120 · Granted Aug 15, 2017

Inventors: Vijay Karamcheti (Palo Alto, CA); Shibabrata Mondal (Bangalore, IN); Swamy Gowda (Bangalore, IN)

Assignee: Virident Systems, LLC

G06F11/2058G06F11/14G06F11/1451G06F11/2082G06F12/0246G06F2201/84G06F2212/7201G06F2212/7202

Abstract

Claims (95)

1. A method comprising:

receiving data for storing in a first asymmetric memory device, wherein latency of read operations is different from latency of write operations in asymmetric memory devices;

identifying a first writing phase as an active writing phase in the first asymmetric memory device, wherein the first asymmetric memory device has at least the first writing phase and a second writing phase that are alternately active, each writing phase associated with a group of segments that are written when a corresponding writing phase is active, wherein a segment includes a logical mapping of physical memory locations in asymmetric memory devices and is associated with a portion of the physical memory locations that is erased in a single operation;

upon the first writing phase being active, writing to a first group of segments that are associated with the first writing phase;

upon the second writing phase being active, writing to a second group of segments that are associated with the second writing phase;

identifying, in the first writing phase as the active writing phase, a first segment in the first group of segments that is available for writing data;

writing the received data to a first memory block that is available in the first segment; and

in connection with writing the received data to the first memory block in the first segment, storing information indicating that the first segment and the first memory block have been written in a latest instance of the first writing phase as the active writing phase.

2. The method of claim 1 , the method further comprising:

receiving, at the first memory device and from a synchronous mirroring module, a first query for information about a segment written in a most recently completed writing phase;

in response to the first query, determining that the first writing phase has most recently completed and the second writing phase is the active writing phase;

based on determining that the first writing phase has most recently completed, retrieving the stored information indicating that the first segment and the first memory block have been most recently written in the first writing phase; and

sending the retrieved information to the synchronous mirroring module,

wherein the synchronous mirroring module forwards, to a second asymmetric memory device, the information indicating that the first segment and the first memory block have been most recently written in the first writing phase, and

wherein the information indicating that the first segment and the first memory block have been most recently written in the first writing phase is recorded in a first marker stored in the second asymmetric memory device, the first marker associated with the first writing phase.

3. The method of claim 2 , further comprising:

sending, by the synchronous mirroring module to the first asymmetric memory device subsequent to sending the first query, a second query for information about which segment has been written in a most recently completed writing phase;

receiving, at the synchronous mirroring module, information indicating that the second writing phase is the most recently completed writing phase, and that a second segment and a second memory block have been most recently written in the second writing phase; and

sending, by the synchronous mirroring module to the second asymmetric memory device, the information indicating that a second segment and a second memory block have been most recently written in the second writing phase,

wherein the information indicating that a second segment and a second memory block have been most recently written in the second writing phase is recorded in a second marker stored in the second asymmetric memory device, the second marker associated with the second writing phase.

4. The method of claim 2 , further comprising:

receiving, at the synchronous mirroring module from the second asymmetric memory device, a message indicating that the second asymmetric memory device has recovered from a stoppage, wherein the message includes a copy of a marker that is recorded by the second asymmetric memory device before the stoppage, the marker identifying a recent segment and memory block written in the first asymmetric memory device;

based on receiving the message, sending, by the synchronous mirroring module to the first asymmetric memory device, a second query for information about segments that have been most recently filled with data;

receiving, at the synchronous mirroring module from the first asymmetric memory device, a response to the second query that includes information about a second segment and a second memory block that have been most recently written in the first asymmetric memory device;

determining, by the synchronous mirroring module, information about the recent segment and the recent memory block from the copy of the marker included in the message;

comparing, by the synchronous mirroring module, information about the recent segment and the recent memory block with the information about the second segment and the second memory block;

based on the comparison, identifying, by the synchronous mirroring module, one or more new segments and new memory blocks written in the first asymmetric memory device that have not been recorded in the second asymmetric memory device;

determining, by the synchronous mirroring module, whether the one or more new segments and new memory blocks represent valid data; and

conditioned on determining that the one or more new segments and new memory blocks represent valid data, sending, by the synchronous mirroring module to the second asymmetric memory device, information about the one or more new segments and new memory blocks.

5. The method of claim 4 , wherein determining whether the one or more new segments and new memory blocks represent valid data comprises determining whether physical memory blocks in the first asymmetric memory device are accurately mapped to logical blocks corresponding to the one or more new segments and new memory blocks.

6. The method of claim 4 , further comprising:

conditioned on determining that at least one of the one or more new segments and new memory blocks do not represent valid data, determining, by the synchronous mirroring module, information about remaining new segments and new memory blocks that represent valid data; and

sending, by the synchronous mirroring module to the second asymmetric memory device, information about the remaining new segments and new memory blocks.

7. The method of claim 4 , wherein the copy of the marker included in the message corresponds to one of the most recent marker recorded by the second asymmetric memory device before the stoppage, or the second most recent marker recorded by the second asymmetric memory device before the stoppage.

8. The method of claim 4 , wherein the message from the second asymmetric memory device indicates that the marker included in the message is associated with the first writing phase,

wherein the second query sent by the synchronous mirroring module includes a request for information about segments that have been most recently filled with data in the first writing phase, and

wherein, the second segment and the second memory block included in the response to the second query are associated with the first writing phase.

9. The method of claim 2 , wherein the stored information indicating that the first segment and the first memory block have been most recently written in the first writing phase is retrieved while data is concurrently written to a second memory block and second segment in the second writing phase.

10. The method of claim 9 , wherein the second segment is same as the first segment, and wherein the second memory block is different from the first memory block.

11. The method of claim 2 , wherein the two or more writing phases that are alternately active further includes a third writing phase, and wherein the second asymmetric memory device is configured to store separate markers associated with the separate writing phases, each marker recording information about a segment and a memory block that are most recently written in the associated writing phase.

12. The method of claim 2 , wherein the second asymmetric memory device is configured to store a marker associated with the two or more writing phases that are alternately active, wherein the marker is configured to record information about segments and memory blocks that are most recently written in the two or more writing phases.

13. A system comprising:

one or more processors; and

instructions stored in a machine-readable medium that, when executed by the one or more processors, are configured to cause the one or more processors to perform operations comprising:

receiving data for storing in a first asymmetric memory device, wherein latency of read operations is different from latency of write operations in asymmetric memory devices;

identifying a first writing phase as an active writing phase in the first asymmetric memory device, wherein the first asymmetric memory device has at least the first writing phase and a second writing phase that are alternately active, each writing phase associated with a group of segments that are written when a corresponding writing phase is active, wherein a segment includes a logical mapping of physical memory locations in asymmetric memory devices and is associated with a portion of the physical memory locations that is erased in a single operation;

upon the first writing phase being active, writing to a first group of segments that are associated with the first writing phase;

upon the second writing phase being active, writing to a second group of segments that are associated with the second writing phase;

identifying, in the first writing phase as the active writing phase, a first segment in the first group of segments that is available for writing data;

writing the received data to a first memory block that is available in the first segment; and

in connection with writing the received data to the first memory block in the first segment, storing information indicating that the first segment and the first memory block have been written in a latest instance of the first writing phase as the active writing phase.

14. The system of claim 13 , wherein the instructions are configured to cause the one or more processors to perform operations further comprising:

receiving, at the first memory device and from a synchronous mirroring module, a first query for information about a segment written in a most recently completed writing phase;

in response to the first query, determining that the first writing phase has most recently completed and the second writing phase is the active writing phase;

based on determining that the first writing phase has most recently completed, retrieving the stored information indicating that the first segment and the first memory block have been most recently written in the first writing phase; and

sending the retrieved information to the synchronous mirroring module,

wherein the synchronous mirroring module forwards, to a second asymmetric memory device, the information indicating that the first segment and the first memory block have been most recently written in the first writing phase, and

wherein the information indicating that the first segment and the first memory block have been most recently written in the first writing phase is recorded in a first marker stored in the second asymmetric memory device, the first marker associated with the first writing phase.

15. The system of claim 14 , wherein the instructions are configured to cause the one or more processors to perform operations further comprising:

sending, by the synchronous mirroring module to the first asymmetric memory device subsequent to sending the first query, a second query for information about which segment has been written in a most recently completed writing phase;

receiving, at the synchronous mirroring module, information indicating that the second writing phase is the most recently completed writing phase, and that a second segment and a second memory block have been most recently written in the second writing phase; and

sending, by the synchronous mirroring module to the second asymmetric memory device, the information indicating that a second segment and a second memory block have been most recently written in the second writing phase,

wherein the information indicating that a second segment and a second memory block have been most recently written in the second writing phase is recorded in a second marker stored in the second asymmetric memory device, the second marker associated with the second writing phase.

16. The system of claim 14 , wherein the instructions are configured to cause the one or more processors to perform operations further comprising:

receiving, at the synchronous mirroring module from the second asymmetric memory device, a message indicating that the second asymmetric memory device has recovered from a stoppage, wherein the message includes a copy of a marker that is recorded by the second asymmetric memory device before the stoppage, the marker identifying a recent segment and memory block written in the first asymmetric memory device;

based on receiving the message, sending, by the synchronous mirroring module to the first asymmetric memory device, a second query for information about segments that have been most recently filled with data;

receiving, at the synchronous mirroring module from the first asymmetric memory device, a response to the second query that includes information about a second segment and a second memory block that have been most recently written in the first asymmetric memory device;

determining, by the synchronous mirroring module, information about the recent segment and the recent memory block from the copy of the marker included in the message;

comparing, by the synchronous mirroring module, information about the recent segment and the recent memory block with the information about the second segment and the second memory block;

based on the comparison, identifying, by the synchronous mirroring module, one or more new segments and new memory blocks written in the first asymmetric memory device that have not been recorded in the second asymmetric memory device;

determining, by the synchronous mirroring module, whether the one or more new segments and new memory blocks represent valid data; and

conditioned on determining that the one or more new segments and new memory blocks represent valid data, sending, by the synchronous mirroring module to the second asymmetric memory device, information about the one or more new segments and new memory blocks.

17. The system of claim 16 , wherein determining whether the one or more new segments and new memory blocks represent valid data comprises determining whether physical memory blocks in the first asymmetric memory device are accurately mapped to logical blocks corresponding to the one or more new segments and new memory blocks.

18. The system of claim 16 , wherein the instructions are configured to cause the one or more processors to perform operations further comprising:

conditioned on determining that at least one of the one or more new segments and new memory blocks do not represent valid data, determining, by the synchronous mirroring module, information about remaining new segments and new memory blocks that represent valid data; and

sending, by the synchronous mirroring module to the second asymmetric memory device, information about the remaining new segments and new memory blocks.

19. The system of claim 16 , wherein the copy of the marker included in the message corresponds to one of the most recent marker recorded by the second asymmetric memory device before the stoppage, or the second most recent marker recorded by the second asymmetric memory device before the stoppage.

20. The system of claim 16 , wherein the message from the second asymmetric memory device indicates that the marker included in the message is associated with the first writing phase,

wherein the second query sent by the synchronous mirroring module includes a request for information about segments that have been most recently filled with data in the first writing phase, and

wherein, the second segment and the second memory block included in the response to the second query are associated with the first writing phase.

21. The system of claim 14 , wherein the stored information indicating that the first segment and the first memory block have been most recently written in the first writing phase is retrieved while data is concurrently written to a second memory block and second segment in the second writing phase.

22. The system of claim 21 , wherein the second segment is same as the first segment, and wherein the second memory block is different from the first memory block.

23. The system of claim 14 , wherein the two or more writing phases that are alternately active further includes a third writing phase, and wherein the second asymmetric memory device is configured to store separate markers associated with the separate writing phases, each marker recording information about a segment and a memory block that are most recently written in the associated writing phase.

24. The system of claim 14 , wherein the second asymmetric memory device is configured to store a marker associated with the two or more writing phases that are alternately active, wherein the marker is configured to record information about segments and memory blocks that are most recently written in the two or more writing phases.

25. A method comprising:

receiving data for storing in a first asymmetric memory device, wherein latency of read operations is different from latency of write operations in asymmetric memory devices and wherein the asymmetric memory device includes a first writing phase and a second writing phase that are alternately active, each writing phase associated with a group of segments that are written when a corresponding writing phase is active, wherein a segment includes a logical mapping of physical memory locations in asymmetric memory devices and is associated with a portion of the physical memory locations that is erased in a single operation;

identifying the first writing phase as an active writing phase in the first asymmetric memory device;

identifying, in the first writing phase, a first segment for writing data;

writing the received data to the first segment;

in connection with writing the received data to the first segment, storing information indicating that the first segment has been most recently written in the first writing phase;

receiving, at the first memory device and from a synchronous mirroring module, a first query for information about a segment written in a most recently completed writing phase;

determining that the first writing phase has most recently completed and the second writing phase is currently active;

in response to receiving the first query and based on determining that the first writing phase has most recently completed, retrieving the information indicating that the first segment has been most recently written in the first writing phase; and

sending the information to the synchronous mirroring module,

wherein the information is recorded in a first marker stored in a second asymmetric memory device, the first marker associated with the first writing phase.

Assignments (13)

Continuity (2)