System and method to enhance solder joint reliability
A reliability cover that is disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package is disclosed. The integrated circuit package is mountable to a printed circuit board via a plurality of solder balls. The reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, and between the Si die and a substrate of the integrated circuit package by a threshold value.
1. A system, comprising:
a reliability cover disposed over at least one of an integrated circuit package and a Si die of the integrated circuit package, wherein the integrated circuit package is mountable to a printed circuit board via a plurality of solder balls, wherein the reliability cover is disposed over the Si die, wherein the reliability cover covers only one or more portions of a top surface area of the Si die, rather than covering the entire top surface area of the Si die,
wherein the reliability cover is configured to reduce a difference in a coefficient of thermal expansion between the integrated circuit package and the printed circuit board, or between the Si die and a substrate of the integrated circuit package by a threshold value, and
wherein the reliability cover is disposed at one or more corners of a top surface of the at least one of the integrated circuit package and the Si die of the integrated circuit package.
2. The system of claim 1 , wherein the reliability cover is deposited as a film.
3. The system of claim 1 , wherein the reliability cover is configured as a mechanical lid.
4. The system of claim 1 , wherein the reliability cover is disposed along at least a portion of a perimeter of the top surface of the at least one of the integrated circuit package and the Si die of the integrated circuit package.
5. The system of claim 1 , wherein the reliability cover is disposed over areas of the integrated circuit package that correspond to a failure profile of solder joints formed between the plurality of solder balls and the integrated circuit package and between the plurality of solder balls and the printed circuit board.
6. The system of claim 1 , wherein the reliability cover comprises one or more reliability cover portions, and each of the one or more reliability cover portions is configured to reduce the difference in the coefficient of thermal expansion between the integrated circuit package and the printed circuit board by varying threshold values.
7. The system of claim 1 , wherein the reliability cover comprises a package level reliability cover that is disposed on at least a portion of the integrated circuit package, and wherein the reliability cover further comprises a die level reliability cover that is disposed on at least a portion of the Si die.
8. The system of claim 1 , wherein the reliability cover comprises a die level reliability cover that is disposed on an interposer layer formed between a substrate of the integrated circuit package and the Si die.
9. The system of claim 1 , wherein the reliability cover is composed of at least one of a copper alloy and an aluminum alloy.
10. The system of claim 1 , wherein a thickness of the reliability cover is scaled based on a height of the integrated circuit package, a coefficient of thermal expansion of the integrated circuit package, and a coefficient of thermal expansion of the reliability cover.
11. The system of claim 1 , further comprising an air release hole on a surface of the reliability cover to vent air pressure from between the reliability cover and the integrated circuit package.
12. A system, comprising:
a printed circuit board having a first coefficient of thermal expansion;
an integrated circuit package configured to be mounted to the printed circuit board and having a second coefficient of thermal expansion; and
a reliability cover disposed over at least a portion of the integrated circuit package and at least a portion of a Si die within the integrated circuit package, wherein the reliability cover does not cover a side area of the Si die and wherein the reliability cover is configured to reduce a difference between the first coefficient of thermal expansion and the second coefficient of thermal expansion by a threshold value,
wherein a second reliability cover is disposed over the integrated circuit package, and the second reliability cover does not cover a side area of the integrated circuit package.
13. The system of claim 12 , further comprising a plurality of solder balls configured to mount the integrated circuit package to the printed circuit board, wherein at least some of the plurality of solder balls are attached to a preform provided on a surface of the printed circuit board, and wherein a combined height of each of the at least some of the plurality of solder balls and the preform is greater than a height of each of the at least some of the plurality of solder balls.
14. The system of claim 1 , wherein the top surface area of the Si die has a perimeter, and the reliability cover does not extend to at least a portion of the perimeter.
15. The system of claim 1 , wherein the reliability cover does not cover a side area of the Si die.
16. The system of claim 12 , wherein the reliability cover does not cover a side area of the integrated circuit package.
17. The system of claim 12 , wherein the reliability cover does not cover at least a portion of a top surface area of the Si die.
18. The system of claim 12 , wherein the reliability cover does not cover any part of all side areas of the integrated circuit package.