LBNs prefetching per CPU
The present disclosure generally relates to prefetching data from one or more CPUs prior to the data being requested by a host device. The prefetched data is prefetched from memory and stored in cache. If a host device requests data that is not already in cache, then a determination is made regarding whether the data is scheduled to be written into cache. If the data is not in cache and is not scheduled to be written into cache, then the data is retrieved from memory and delivered to the host device. If the data is scheduled to be written into cache, or is currently being written into cache, then the request to retrieve the data is delayed or scheduled to retrieve the data once the data is in cache. If the data is already in cache, the data is delivered to the host device.
1. A system, comprising:
a memory system, the memory system comprising:
a first CPU;
at least one additional CPU;
a memory device coupled to both the first CPU and the at least one additional CPU; and
a controller coupled to the memory system, the controller configured to:
receive a first request from a host device to read a first data and a second request to read a second data from a memory device that is coupled to a plurality of CPUs, wherein a first CPU of the plurality of CPUs has a first cache storage and a second CPU of the plurality of CPUs has a second cache storage;
read the first data from the memory device using the first CPU;
read the second data from the memory device using the second CPU of the plurality of CPUs;
write the first data and the second data to the first cache storage of the first CPU;
read the first and second data from the first cache storage; and
deliver the first and second data to the host device.
2. The system of claim 1 , wherein the memory device is a NAND storage device.
3. The system of claim 1 , wherein the memory device is a hard disk drive storage device.
4. A system of claim 1 , wherein the controller is further configured to:
receive a second request from a host device to read a first LBA data from a first LBN and a second LBN disposed in the memory device that is coupled to the first CPU and the second CPU, wherein the first CPU has a first cache storage and is assigned the first_LBN, wherein the second CPU has a second cache storage and is assigned the second LBN;
read a first portion of the first LBA data from the first LBN of the memory device;
read a second portion of the first LBA data from the second LBN of the memory device;
write the first portion of the first LBN data and the second portion of the first LBN data to the first cache storage;
read the first LBA data from the first cache storage; and
deliver the first LBA data to the host device.
5. The system of claim 4 , wherein the controller is further configured to:
receive a third request from the host device to read a second LBA data from the memory device, wherein the first LBA data and the second LBA data are sequential data;
read the second LBA data from the memory device;
write the second LBA data to the first cache storage; and
deliver the second LBA data to the host device.
6. The system of claim 5 , wherein the writing the second LBA data to the first cache storage occurs prior to receiving the second request.
7. The system of claim 4 , wherein the reading the first portion of the first LBA data is performed by the first CPU and reading the second portion of the first LBA data is performed by the second CPU.
8. The system of claim 1 , wherein the controller is configured to determine whether the first data is disposed in the first cache storage.
9. The system of claim 8 , wherein the controller is configured to deliver the first data to a host device upon determining that the first data is in the first cache storage.
10. The system of claim 9 , wherein the controller is further configured to read the first data from the first cache storage.
11. The system of claim 8 , wherein the controller is configured to read the first data from the memory device upon determining that the first data is not disposed in the first cache storage.
12. The system of claim 11 , wherein the controller is configured to write the first data into the first cache storage.
13. The system of claim 12 , wherein the controller is configured to deliver the first data to a host device from the first cache storage.
14. The system of claim 1 , wherein the controller is configured to prefetch LBA data.
15. The system of claim 14 , wherein the controller is configured to determine whether the LBA data begins and ends on LBN boundaries.
16. The system of claim 15 , wherein the controller is configured to read LBA data from the memory device upon determining that the LBA data begins and ends on the LBN boundaries.
17. The system of claim 16 , wherein the controller is configured to write the LBA data to the first cache storage.
18. The system of claim 15 , wherein the controller is configured to determine how many additional read commands are necessary for the LBA data to end on a LBN boundary upon determining that the LBA data does not being and end on the LBN boundaries.
19. The system of claim 18 , wherein the controller is configured to calculate a number of whole LBNs that are needed to be cached to handle the determined additional read commands.
20. The system of claim 19 , wherein the controller is configured to determine remaining LBNs that could be fit into the first cache storage.