Integrated electronic element module, semiconductor package, and method for fabricating the same
A substrate-less integrated electronic element module for a semiconductor package, comprising: at least two electronic elements, each of the at least two electronic elements having first electrical connectors; and a first molding compound encapsulating the at least two electronic elements, the first molding compound comprising a first planar surface and an opposing second planar surface of the integrated electronic element module, wherein each of the first electrical connectors is directly exposed on the first planar surface of the integrated electronic element module. Further, a semiconductor package including the integrated electronic element module and the method of fabricating the same is provided.
1. A semiconductor package, comprising:
a substrate-less integrated electronic element module, comprising:
at least two electronic elements, each of the at least two electronic elements having first electrical connectors, the electrical connectors comprising one or more of contact pads and conductive bumps and
a first molding compound encapsulating the at least two electronic elements, the first molding compound comprising a first planar surface and an opposing second planar surface;
a plurality of semiconductor dies comprising second electrical connectors; and
a second molding compound encapsulating the substrate-less integrated electronic element module and the one or more semiconductor dies, the second molding compound comprising a third planar surface;
wherein each of the first electrical connectors and the second electrical connectors are directly exposed on the third planar surface of the second molding compound; and
wherein the at least two electronic elements are encapsulated inside both the first molding compound and the second molding compound, and
wherein the plurality of semiconductor dies are encapsulated once inside the second molding compound.
2. The integrated electronic element module according to claim 1 , wherein the at least two electronic elements comprise a combination of one or more of the following: a multi-layered ceramic capacitor, a silicon-based capacitor, a resistor, an inductor, an application specific integrated circuit die, a general purpose integrated circuit die, a wafer-level chip-scale package (WLCSP), and a quad flat no-lead package low dropout (QFN/LDO).
3. The integrated electronic element module according to claim 1 , wherein the first electrical connectors comprise contact pads and conductive bumps formed only on a part of the first electrical connectors, wherein top surfaces of the conductive bumps and top surfaces of the first electrical connectors without the conductive bumps formed thereon are all coplanar with each other.
4. The integrated electronic element module according to claim 1 , wherein the first electrical connectors comprise contact pads and conductive bumps formed on each of the first electrical connectors, wherein top surfaces of the conductive bumps are all coplanar with each other.
5. The integrated electronic element module according to claim 1 , wherein the first electrical connectors have a gap smaller than 10 μm between closest adjacent first electrical connectors.
6. A semiconductor package, comprising:
an integrated electronic element module, comprising:
at least two electronic elements, each of the at least two electronic elements having first electrical connectors; and
a first molding compound encapsulating the at least two electronic elements, the first molding compound comprising a first planar surface and an opposing second planar surface, each of the at least two electronic components mounted adjacent the first planar surface and each of the first electrical connectors exposed at the first planar surface;
a semiconductor device comprising second electrical connectors;
a second molding compound encapsulating the integrated electronic element module and the semiconductor device, the second molding compound comprising a third planar surface and an opposing fourth planar surface, the third planar surface being closer to the first planar surface than the second planar surface; and
a redistribution layer formed over the third planar surface;
wherein each of the first electrical connectors is directly exposed on the first planar surface, and is electrically connected to the redistribution layer, and
wherein each of the second electrical connectors of the semiconductor device extends to the third planar surface, and is electrically connected to the redistribution layer.
7. The semiconductor package according to claim 6 , wherein the semiconductor package is substrate-less.
8. The semiconductor package according to claim 6 , wherein the at least two electronic elements comprise a combination of one or more of the following: a multi-layered ceramic capacitor, a silicon-based capacitor, a resistor, and inductor, an application specific integrated circuit die, a general purpose integrated circuit die, a wafer-level chip-scale package (WLCSP), and a quad flat no-lead package low dropout (QFN/LDO).
9. The semiconductor package according to claim 6 , wherein the integrated electronic element module further comprises conductive bumps formed only on a part of the first electrical connectors, wherein top surfaces of the conductive bumps and top surfaces of each of the first electrical connectors without conductive bumps formed thereon are all coplanar with each other.
10. The semiconductor package according to claim 6 , wherein the integrated electronic element module further comprises conductive bumps formed on each of the first electrical connectors, wherein top surfaces of the conductive bumps are all coplanar with each other.
11. The semiconductor package according to claim 6 , wherein the first electrical connectors have a gap smaller than 10 μm between closest adjacent first electrical connectors.
12. The semiconductor package according to claim 6 , wherein the semiconductor device comprises a plurality of stacked memory dies.
13. The semiconductor package according to claim 12 , wherein the integrated electronic element module and the semiconductor device are disposed over the redistribution layer in a side-by-side manner.
14. The semiconductor package according to claim 13 , wherein a thickness of the integrated electronic element module and the second molding compound of the semiconductor package have the same thickness.
15. The semiconductor package according to claim 13 , further comprising a spacer disposed on a side of the integrated electronic element module facing away from the redistribution layer, and wherein a sum of a thickness of the integrated electronic element module and a thickness of the spacer equals to a thickness of the second molding compound of the semiconductor package.
16. The semiconductor package according to claim 12 , wherein the integrated electronic element module is mounted next to the semiconductor device.
17. The semiconductor package according to claim 6 , further comprising a third molding compound formed on the fourth planar surface.
18. A semiconductor package, comprising:
an integrated electronic element module, comprising:
at least two electronic elements, each of the at least two electronic elements having first electrical connectors; and
a first molding compound encapsulating the at least two electronic elements, the first molding compound comprising a first planar surface and an opposing second planar surface;
a semiconductor device comprising second electrical connectors;
a second molding compound encapsulating the integrated electronic element module and the semiconductor device, the second molding compound comprising a third planar surface and an opposing fourth planar surface, the third planar surface being closer to the first planar surface than the second planar surface; and
a redistribution layer formed over the third planar surface;
wherein each of the first electrical connectors is directly exposed on the first planar surface, and is electrically connected to the redistribution layer, and
wherein each of the second electrical connectors of the semiconductor device extends to the third planar surface, and is electrically connected to the redistribution layer, and
wherein the integrated electronic element module and the semiconductor device are disposed over the redistribution layer in a side-by-side manner, and
wherein a thickness of the integrated electronic element module and the second molding compound of the semiconductor package have the same thickness.