IP Library Granted Patent US 12,013,753
Granted Patent B2
US 12,013,753 · App. 17/752,771 · Granted Jun 18, 2024

Proactive loss notification and handling in data storage devices

Inventors: Bhavya Krishna (Ernakulam, IN); Ramanathan Muthiah (Bangalore, IN)
Assignee: Western Digital Technologies, Inc.
G06F11/106G06F11/0727G06F11/1004G06F11/1076
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Quick Facts
Patent No.
US 12,013,753
App. No.
17/752,771
Granted
Jun 18, 2024
Kind
B2
Abstract

Devices, systems, and methods with proactive data loss notification and handling. A data storage device includes a memory and a controller. The controller includes a processor and controller memory. The controller memory stores a set of instructions that, when executed by the processor, instruct the controller to: detect an uncorrectable error correction code (UECC) during an internal data movement process of the storage device memory, modify a metadata field associated with a logical block address corresponding to the UECC, inform a host device about the UECC, and determine whether data stored in at least one adjacent region to the logical block address is lost.

Claims (51)

1. A data storage device comprising:

a non-volatile memory; and

a controller comprising an electronic processor and a controller memory, the controller memory storing a set of instructions that, when executed by the electronic processor, instruct the controller to:

detect, with the electronic processor, an uncorrectable error correction code (UECC) during an internal data movement process of the non-volatile memory,

modify a metadata field associated with a logical block address (LBA) corresponding to the UECC,

inform an external electronic device about the UECC, and

determine whether data stored in at least one adjacent region to the LBA is lost.

2. The data storage device of claim 1 , wherein the internal data movement process is a garbage collection process, a wear levelling process, or a read scrub process.

3. The data storage device of claim 1 , wherein, when the electronic processor determines that the data stored in the at least one adjacent region is lost, the instructions further instruct the controller to:

translate a physical address of the at least one adjacent region to a second LBA corresponding to the at least one adjacent region, and

inform the external electronic device that the data stored in the at least one adjacent region is lost.

4. The data storage device of claim 3 , wherein translating the physical address to the second LBA is based on a reverse mapping operation.

5. The data storage device of claim 1 , wherein, when the electronic processor determines that the data stored in the at least one adjacent region is not lost, the instructions further instruct the controller to process a command received from the external electronic device.

6. The data storage device of claim 1 , wherein the non-volatile memory is a NAND memory.

7. The data storage device of claim 1 , wherein the instructions further instruct the controller to:

receive, from the external electronic device, lost data associated with the LBA corresponding to the UECC; and

write the lost data to the non-volatile memory.

8. The data storage device of claim 7 , wherein writing the lost data to the non-volatile memory includes receiving, from an external electronic device, a new write command to write the lost data to the LBA corresponding to the UECC.

9. A method of handling data loss, the method comprising:

detecting, with an electronic processor, an uncorrectable error correction code during an internal data movement process of a data storage device;

modifying a metadata field associated with a logical block address corresponding to the UECC;

informing an external electronic device about the UECC; and

determining whether data stored in at least one adjacent region to the LBA is lost.

10. The method of claim 9 , wherein the internal data movement process is a garbage collection process, a wear levelling process, or a read scrub process.

11. The method of claim 9 , wherein, when the data stored in the at least one adjacent region is lost, the method further comprises:

translating a physical address of the at least one adjacent region to a second LBA corresponding to the at least one adjacent region; and

informing the external electronic device that the data stored in the at least one adjacent region is lost.

12. The method of claim 11 , wherein translating the physical address to the second LBA is based on a reverse mapping operation.

13. The method of claim 9 , wherein, when the data stored in the at least one adjacent region is not lost, the method further comprises processing a command received from the external electronic device.

14. A data storage system comprising:

a data storage device including a memory controller and a memory, the memory controller including an electronic processor and a controller memory; and

an external electronic device including an external electronic device processor and an external electronic device memory;

wherein the controller memory stores a set of instructions that, when executed by the electronic processor, instruct the data storage device to:

detect, with the electronic processor, an uncorrectable error correction code during an internal data movement process of the data storage device,

modify a metadata field associated with a logical block address corresponding to the UECC,

generate a notification to be sent to the external electronic device about the UECC, and

determine whether data stored in at least one adjacent region to the LBA is lost.

15. The data storage system of claim 14 , wherein the internal data movement process is a garbage collection process, a wear levelling process, or a read scrub process.

16. The data storage system of claim 14 , wherein, when the electronic processor determines that the data stored in the at least one adjacent region is lost, the instructions further instruct the data storage device to:

translate a physical address of the at least one adjacent region to a second LBA corresponding to the at least one adjacent region based on a reverse mapping operation, and

inform the external electronic device that the data stored in the at least one adjacent region is lost.

17. The data storage system of claim 14 , wherein, when the electronic processor determines that the data stored in the at least one adjacent region is not lost, the instructions further instruct the data storage device to process a command received from the external electronic device.

18. The data storage system of claim 14 , wherein the external electronic device memory stores a set of instructions that, when executed by the external electronic device processor, instruct the external electronic device to:

receive, with the external electronic device processor, the notification from the electronic processor about the UECC, and

check, with the external electronic device processor, whether the data storage device includes a redundant array of independent disks (RAID) mechanism.

19. The data storage system of claim 18 , wherein, when the external electronic device processor determines that the data storage device includes the RAID mechanism, the instructions further instruct the external electronic device to:

trigger, with the external electronic device processor, the RAID mechanism to recover the data stored in the LBA, and

write, with the external electronic device processor, the data to the data storage device.

20. The data storage system of claim 18 , wherein, when the external electronic device processor determines that the data storage device does not include a RAID mechanism, the instructions further instruct the external electronic device to:

circumvent the UECC, and

reconstruct the data stored in the LBA.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2022
From: KRISHNA, BHAVYA; MUTHIAH, RAMANATHAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060007/0213 →