Granted Patent B1

US 11,456,758 · App. 17/239,057 · Granted Sep 27, 2022

Inventors: Ran Zamir (Ramat Gan, IL); Eran Sharon (Rishon Lezion, IL); Alexander Bazarsky (Holon, IL)

Assignee: Western Digital Technologies, Inc.

H03M13/353G06F11/1076G11C16/26H03M7/3059G11C16/0483

Abstract

Claims (60)

1. A memory, comprising:

one or more storage elements;

compressed soft-bit circuitry configured to:

determine a soft-bit delta and one compression scheme of a plurality of compression schemes based on one or more conditions of the one or more storage elements;

read/write circuitry configured to:

read a set of hard bits from the one or more storage elements, and

sense a first set of soft-bits using the determined soft-bit delta while reading the set of hard bits from the one or more storage elements, the first set of soft-bits having a first fixed size, and each soft-bit of the first set of soft-bits indicating a reliability of a corresponding hard bit of the set of hard bits,

wherein the compressed soft-bit circuitry is further configured to:

receive the first set of soft-bits,

generate a second set of soft-bits from the first set of soft-bits based on the one compression scheme that is determined, and

output the second set of soft-bits.

2. The memory of claim 1 , wherein the compressed soft-bit circuitry is further configured to:

determine the one or more conditions of the one or more storage elements,

wherein the one or more conditions is a first bit error rate (BER) below a first threshold, wherein, to determine the soft-bit delta and the one compression scheme based on the one or more conditions, the compressed soft-bit circuitry is further configured to determine that the one compression scheme is a first fixed lossy compression scheme, and wherein the second set of soft-bits have a second fixed size that is smaller than the first fixed size.

3. The memory of claim 2 , wherein the one or more conditions is a second bit error rate (BER) at or above the first threshold and below a second threshold, wherein, to determine the soft-bit delta and the one compression scheme based on the one or more conditions, the compressed soft-bit circuitry is further configured to determine that the one compression scheme is a second fixed lossy compression scheme, and wherein the second set of soft-bits have a third fixed size that is smaller than the first fixed size and larger than the second fixed size.

4. The memory of claim 3 , wherein the one or more conditions is a third bit error rate (BER) at or above the second threshold, wherein, to determine the soft-bit delta and the one compression scheme based on the one or more conditions, the compressed soft-bit circuitry is further configured to determine that the one compression scheme is a third fixed lossy compression scheme, and wherein the second set of soft-bits have a fourth fixed size that is smaller than the first fixed size and larger than the second fixed size and the third fixed size.

5. The memory of claim 1 , wherein the compressed soft-bit circuitry is further configured to:

determine the one or more conditions of the one or more storage elements,

wherein the one or more conditions is a first bit error rate (BER) at or above a zero compression threshold, wherein, to determine the soft-bit delta and the one compression scheme based on the one or more conditions, the compressed soft-bit circuitry is further configured to determine that the one compression scheme is a zero compression scheme, and wherein the second set of soft-bits have a second fixed size that is the same as the first fixed size.

6. The memory of claim 1 , wherein the compressed soft-bit circuitry is further configured to:

determine the one or more conditions of the one or more storage elements,

wherein the one or more conditions is a first bit error rate (BER) below a first threshold, wherein, to determine the soft-bit delta and the one compression scheme based on the one or more conditions, the compressed soft-bit circuitry is further configured to determine that the one compression scheme is a first variable lossless compression scheme, and wherein the second set of soft-bits have a second fixed size that is smaller than the first fixed size.

7. The memory of claim 6 , wherein the one or more conditions is a second bit error rate (BER) at or above the first threshold and below a second threshold, wherein, to determine the soft-bit delta and the one compression scheme based on the one or more conditions, the compressed soft-bit circuitry is further configured to determine that the one compression scheme is a first fixed lossy compression scheme, and wherein the second set of soft-bits have a third fixed size that is smaller than the first fixed size and larger than the second fixed size.

8. A method comprising:

determining, with compressed soft-bit circuitry, a soft-bit delta and one compression scheme of a plurality of compression schemes based on one or more conditions of one or more storage elements;

reading, with read/write circuitry, a set of hard bits from the one or more storage elements;

sensing, with the compressed soft-bit circuitry, a first set of soft-bits using the determined soft-bit delta while reading the set of hard bits from the one or more storage elements, the first set of soft-bits having a first fixed size, and each soft-bit of the first set of soft-bits indicating a reliability of a corresponding hard bit of the set of hard bits;

receiving, with the compressed soft-bit circuitry, the first set of soft-bits;

generating, with the compressed soft-bit circuitry, a second set of soft-bits from the first set of soft-bits based on the one compression scheme that is determined; and

outputting the second set of soft-bits.

9. The method of claim 8 , further comprising:

determining, with the compressed soft-bit circuitry, the one or more conditions of the one or more storage elements,

wherein the one or more conditions is a first bit error rate (BER) below a first threshold, wherein determining the soft-bit delta and the one compression scheme based on the one or more conditions further includes determining that the one compression scheme is a first fixed lossy compression scheme based on the first BER, and wherein the second set of soft-bits have a second fixed size that is smaller than the first fixed size.

10. The method of claim 9 , wherein the one or more conditions is a second BER at or above the first threshold and below a second threshold, wherein determining the soft-bit delta and the one compression scheme based on the one or more conditions further includes determining that the one compression scheme is a second fixed lossy compression scheme based on the second BER, and wherein the second set of soft-bits have a third fixed size that is smaller than the first fixed size and larger than the second fixed size.

11. The method of claim 10 , wherein the one or more conditions is a third BER at or above the second threshold, wherein determining the soft-bit delta and the one compression scheme based on the one or more conditions further includes determining that the one compression scheme is a third fixed lossy compression scheme based on the third BER, and wherein the second set of soft-bits have a fourth fixed size that is smaller than the first fixed size and larger than the second fixed size and the third fixed size.

12. The method of claim 8 , further comprising:

determining, with the compressed soft-bit circuitry, the one or more conditions of the one or more storage elements,

wherein the one or more conditions is a first bit error rate (BER) at or above a zero compression threshold, wherein determining the soft-bit delta and the one compression scheme based on the one or more conditions further includes determining that the one compression scheme is a zero compression scheme based on the first BER, and wherein the second set of soft-bits have a second fixed size that is the same as the first fixed size.

13. The method of claim 8 , further comprising:

determining, with the compressed soft-bit circuitry, the one or more conditions of the one or more storage elements,

wherein the one or more conditions is a first bit error rate (BER) below a first threshold, wherein determining the soft-bit delta and the one compression scheme based on the one or more conditions further includes determining that the one compression scheme is a variable lossless compression scheme based on the first BER, and wherein the second set of soft-bits have a second fixed size that is smaller than the first fixed size.

14. The method of claim 13 , wherein the one or more conditions is a second BER at or above the first threshold and below a second threshold, wherein determining the soft-bit delta and the one compression scheme based on the one or more conditions further includes that the one compression scheme is a first fixed lossy compression scheme based on the second BER, and wherein the second set of soft-bits have a third fixed size that is smaller than the first fixed size and larger than the second fixed size.

15. The method of claim 8 , further comprising:

determining a soft-bit page quality with respect to compression errors; and

adjusting log-likelihood-ratios (LLRs) based on the soft-bit page quality with respect to the compression errors.

16. An apparatus comprising:

means for determining a soft-bit delta and one compression scheme of a plurality of compression schemes based on one or more conditions of one or more storage elements;

means for reading a set of hard bits from the one or more storage elements;

means for sensing a first set of soft-bits using the determined soft-bit delta while reading the set of hard bits from the one or more storage elements, the first set of soft-bits having a first fixed size, and each soft-bit of the first set of soft-bits indicating a reliability of a corresponding hard bit of the set of hard bits;

means for receiving the first set of soft-bits;

means for generating a second set of soft-bits from the first set of soft-bits based on the one compression scheme that is determined; and

means for outputting the second set of soft-bits.

17. The apparatus of claim 16 , further comprising:

means for determining the one or more conditions of the one or more storage elements,

wherein the one or more conditions is a first bit error rate (BER) below a first threshold, wherein the means for determining the soft-bit delta and the one compression scheme based on the one or more conditions further includes a means for determining that the one compression scheme is a first fixed lossy compression scheme based on the first BER, and wherein the second set of soft-bits have a second fixed size that is smaller than the first fixed size.

18. The apparatus of claim 17 , wherein the one or more conditions is a second BER at or above the first threshold and below a second threshold, wherein the means for determining the soft-bit delta and the one compression scheme based on the one or more conditions further includes a means for determining that the one compression scheme is a second fixed lossy compression scheme based on the second BER, and wherein the second set of soft-bits have a third fixed size that is smaller than the first fixed size and larger than the second fixed size.

19. The apparatus of claim 18 , wherein the one or more conditions is a third BER at or above the second threshold, wherein the means for determining the soft-bit delta and the one compression scheme based on the one or more conditions further includes a means for determining that the one compression scheme is a third fixed lossy compression scheme based on the third BER, and wherein the second set of soft-bits have a fourth fixed size that is smaller than the first fixed size and larger than the second fixed size and the third fixed size.

20. The apparatus of claim 16 , further comprising:

means for determining a soft-bit page quality with respect to compression errors; and

means for adjusting Log-Likelihood-Ratios (LLRs) based on the soft-bit page quality with respect to the compression errors.

Assignments (10)