IP Library Granted Patent US 9,929,213
Granted Patent B2
US 9,929,213 · App. 15/007,965 · Granted Mar 27, 2018

Nano-particle matrix for 3D NVM RRAM

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Quick Facts
Patent No.
US 9,929,213
App. No.
15/007,965
Granted
Mar 27, 2018
Kind
B2
Abstract

The present disclosure generally relates to a nano-particle matrix in a 3D NVM RRAM device. The RRAM device utilizes a material that may be deposited into high aspect ratio channels, has good cycle ability, short erase and write times, and write/erase voltages that are compatible with CMOS. The RRAM material is disposed between two electrodes of the device and includes conductive nano-particles that are distributed within an insulating matrix. The particles are distributed below the percolation threshold.

Claims (45)

1. A non-volatile memory device, comprising:

a first electrode;

a second electrode; and

a first memory material disposed between the first electrode and the second electrode, wherein the first memory material comprises an insulating material having a plurality of metallic nano-particles distributed within the insulating material, wherein the nano-particles are distributed below the percolation threshold, and wherein the metallic nano-particles are selected from the group consisting of palladium, platinum, rhodium, ruthenium, zirconium, tin, molybdenum, chromium, tantalum, hafnium, vanadium, and alloys, wherein the first memory material comprises nano-particles having a composition on a surface of the nano-particles which differ from a composition in an interior of the nano-particles, the surface of the nano-particles comprising a material selected from the group consisting of silicon, germanium, boron, nitrogen, oxygen, palladium, platinum, rhodium, ruthenium, nickel, gold, silver, aluminum, titanium, tungsten, zirconium, tin, molybdenum, chromium, tantalum, hafnium, vanadium, and alloys thereof.

2. The non-volatile memory device of claim 1 , wherein the first electrode is substantially perpendicular to the second electrode.

3. The non-volatile memory device of claim 1 , further comprising:

a third electrode extending substantially parallel to the first electrode;

a fourth electrode extending substantially parallel to the second electrode;

a second memory material disposed between the first electrode and the fourth electrode; and

a third memory material disposed between the third electrode and the second electrode.

4. The non-volatile memory device of claim 3 , wherein the second memory material and the third memory material each comprise an insulating material having a plurality of metallic nano-particles distributed within the insulating material, wherein the nano-particles are distributed below the percolation threshold, and wherein the metallic nano-particles are selected from the group consisting of palladium, platinum, rhodium, ruthenium, nickel, gold, silver, aluminum, titanium, tungsten, zirconium, tin, molybdenum, chromium, tantalum, hafnium, vanadium, and alloys thereof.

5. The non-volatile memory device of claim 1 , further comprising a first nucleation layer disposed between the first electrode and the first memory material.

6. The non-volatile memory device of claim 5 , wherein the nucleation layer comprises:

the same material as the nano-particle material; or

a different material than the nano-particle material; or

a material having a lower surface energy than the nano-particle material; or

the nucleation layer has a surface topography having a surface roughness which is larger on a surface perpendicular to an interface with the first electrode than a surface in contact with the first electrode; or

the nucleation layer has a high density of defects in the surface facing the matrix.

7. A non-volatile memory device, comprising:

a substrate;

a first insulating layer disposed over the substrate;

a first electrode layer disposed on the first insulating layer;

a second insulating layer disposed on the first electrode layer;

a second electrode layer disposed on the second insulating layer;

a third insulating layer disposed on the second electrode layer, wherein a trench is formed through the third insulating layer, the second electrode layer, the second insulating layer, the first electrode layer and the first insulating layer to expose a portion of the substrate;

a memory material layer disposed within the trench, wherein the memory material comprises an insulating material having a plurality of metallic nano-particles distributed within the insulating material, wherein a substantial number of the nano-particles are distributed below the percolation threshold, and wherein the metallic nano-particles are selected from the group consisting of palladium, platinum, rhodium, ruthenium, nickel, gold, silver, aluminum, titanium, tungsten, zirconium, tin, molybdenum, chromium, tantalum, hafnium, vanadium, and alloys thereof; and

a plurality of upper electrodes disposed in physical contact on the memory material layer.

8. The non-volatile memory device of claim 7 , wherein the insulating material is selected from the group consisting of SiO x , SiN x , AlO x , AlN x , TiN x , TiO x , TaO x , TaN x , WO x , WN x , ZrO x , and HfO x , complex oxides, complex nitrides, and complex oxynitrides.

9. The non-volatile memory device of claim 7 , wherein the upper electrodes are substantially perpendicular to the first electrode and the second electrode.

10. The non-volatile memory device of claim 7 , wherein the memory material layer is disposed within a trench.

11. The non-volatile memory device of claim 7 , wherein the memory material comprises a dopant dispersed therein.

12. The non-volatile memory device of claim 11 , wherein the nano-particles further comprise a material selected from the group consisting of silicon, germanium, boron, nitrogen, oxygen, palladium, platinum, rhodium, ruthenium, nickel, gold, silver, aluminum, titanium, tungsten, zirconium, tin, molybdenum, chromium, tantalum, hafnium, vanadium, and alloys thereof.

13. A method of manufacturing a non-volatile memory device, comprising:

depositing a memory material over a first electrode, wherein the first memory material comprises an insulating material having a plurality of metallic nano-particles distributed within the insulating material, wherein the nano-particles are distributed below a percolation threshold, and wherein the metallic nano-particles are selected from the group consisting of palladium, platinum, rhodium, ruthenium, nickel, gold, silver, aluminum, titanium, tungsten, zirconium, tin, molybdenum, chromium, tantalum, hafnium, vanadium, and alloys thereof; and wherein the depositing comprises atomic layer deposition or chemical vapor deposition; and

forming a plurality of upper electrodes in physical contact with the memory material.

14. The method of claim 13 , wherein the memory material further comprises a non-metallic element.

15. The method of claim 13 , wherein the insulating material is selected from the group consisting of SiO x , SiN x , AlO x , AlN x , TiN x , TiO x , TaO x , TaN x , WO x , WN x , ZrO x , and HfO x , complex oxides, complex nitrides, and complex oxynitrides.

16. A 3D non-volatile memory device, comprising:

a plurality of conductive layers alternating with a plurality of insulating layers, wherein the plurality of conductive layers and plurality of insulating layers are disposed over a substrate, wherein a trench is formed through the plurality of conductive layers and plurality of insulating layers to expose the substrate;

a memory material disposed within the trench along the plurality of conductive layers and the plurality of insulating layers, wherein the memory material comprises an insulating material having a plurality of metallic nano-particles distributed within the insulating material, wherein the nano-particles are distributed below a percolation threshold, and wherein the metallic nano-particles are selected from the group consisting of palladium, platinum, rhodium, ruthenium, nickel, gold, silver, aluminum, titanium, tungsten, zirconium, tin, molybdenum, chromium, tantalum, hafnium, vanadium, and alloys thereof; and

a plurality of electrodes disposed in physical contact on the memory material.

17. The 3D non-volatile memory device of claim 16 , wherein the insulating material is selected from the group consisting of SiO x , SiN x , AlO x , AlN x , TiN x , TiO x , TaO x , TaN x , WO x , WN x , ZrO x , and HfO x , complex oxides, complex nitrides, and complex oxynitrides.

18. The 3D non-volatile memory device of claim 16 , further comprising a first nucleation layer disposed between the plurality of conductive layers and the memory material.

19. The 3D non-volatile memory device of claim 18 , wherein the nucleation layer comprises the same material as the nano-particle material or a different material than the nano-particle material or a material having a lower surface energy than the nano-particle material or the nucleation layers may have a surface topography having a surface roughness which is larger on the side facing layer than the opposite sides facing materials or may have a high density of defects in their surface.

20. The 3D non-volatile memory device of claim 18 , wherein the memory material comprises nano-particles having a composition or properties on the surface of the nano-particles which differ from the composition or properties in the interior of the nano-particles.

Assignments (12)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
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To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
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From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
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PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
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PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT SERIAL NO 15/025,946 PREVIOUSLY RECORDED AT REEL: 040831 FRAME: 0265. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 15, 2017
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2016
From: READ, JOHN C.; RUBIN, KURT ALLAN
To: HGST NETHERLANDS B.V.
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