IP Library Granted Patent US 11,934,700
Granted Patent B2
US 11,934,700 · App. 17/720,106 · Granted Mar 19, 2024

Fused command handling

Inventors: Rahul Jain (Karnataka, IN); Arvind Kumar V M (Karnataka, IN)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/0659G06F3/0614G06F3/0673G06F12/0223
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Quick Facts
Patent No.
US 11,934,700
App. No.
17/720,106
Granted
Mar 19, 2024
Kind
B2
Abstract

Aspects of a storage device are provided that handle pairing and atomic processing of fused commands received from submission queues based on data structures such as a linked lists which the controller respectively associates with each submission queue. A memory of the storage device includes a plurality of data structures each associated with a different submission queue. A controller of the storage device receives a first command for a fused operation from a submission queue, stores the first command in a data structure, receives a second command for the fused operation from the submission queue, determines whether the second command corresponds to the fused operation, stores the second command in the data structure in response to the determination, and performs the fused operation in response to storing the second command. As a result, fused command handling may be achieved with minimal impact to queue arbitration logic and command latency.

Claims (66)

1. A storage device, comprising:

a memory including a data structure, wherein the data structure is associated with a submission queue; and

one or more processors coupled to the memory, the one or more processors, individually or in combination, configured to:

receive a first command for a fused operation from the submission queue,

store the first command in the data structure,

receive a second command from the submission queue,

determine whether the second command corresponds to the fused operation,

determine whether a first logical address range indicated in the first command is same as a second logical address range indicated in the second command,

store the second command in the data structure in response to determining that the second command corresponds to the fused operation and that the first logical address range and the second logical address range are the same, and

perform the fused operation in response to storing the second command.

2. The storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to:

prior to receiving the second command, receive a third command for a different operation from the submission queue,

determine whether the third command corresponds to the fused operation, and

in response to a determination that the third command does not correspond to the fused operation, perform the different operation prior to the fused operation.

3. The storage device of claim 2 , wherein the one or more processors, individually or in combination, are further configured to:

determine whether a third logical address range indicated in the third command at least partially overlaps with the first logical address range indicated in the first command for the fused operation, and

in response to determining that the first logical address range and the third logical address range do not overlap, perform the different operation prior to the fused operation.

4. The storage device of claim 2 , wherein the one or more processors, individually or in combination, are further configured to:

determine whether a third logical address range indicated in the third command at least partially overlaps with the first logical address range indicated in the first command for the fused operation, and

in response to a determination that the first logical address range and the third logical address range at least partially overlap, abort the fused operation.

5. The storage device of claim 1 , wherein the memory includes a plurality of data structures including the data structure, and each of the data structures is associated with a different submission queue.

6. The storage device of claim 5 , wherein the one or more processors, individually or in combination, are further configured to:

report to a host device an indication that the storage device supports a smaller number of fused operation commands than a maximum number of the data structures in the memory.

7. The storage device of claim 6 , wherein the first command is a current command, and the one or more processors, individually or in combination, are further configured to:

determine that a current number of stored fused operation commands is equal to the smaller number of fused operation commands, and

in response to a fused operation command in one of the data structures including an earlier timestamp than the current command, replace the fused operation command with the current command in the one of the data structures.

8. The storage device of claim 1 , wherein the one or more processors, individually or in combination, are further configured to:

from a time when the first command is received from the submission queue until a time when the first command is stored in the data structure, prevent reception of subsequent commands including an overlapping logical address range with the first command.

9. A storage device, comprising:

a memory including a data structure, wherein the data structure is associated with a submission queue; and

one or more processors coupled to the memory, the one or more processors, individually or in combination, configured to:

receive a first command for a fused operation from the submission queue, the first command indicating a first logical address range,

store the first command in the data structure,

receive a second command for a different operation from the submission queue, the second command indicating a second logical address range,

determine whether the second command corresponds to the fused operation,

in response to determining that the second command does not correspond to the fused operation, perform the different operation prior to the fused operation,

receive a third command from the submission queue, the third command indicating a third logical address range,

determine whether the third command corresponds to the fused operation and the third logical address range overlaps with the first logical address range, and

in response to determining that the third command corresponds to the fused operation and that the third logical address range overlaps with the first logical address range, store the third command in the data structure and perform the fused operation.

10. The storage device of claim 9 , wherein the one or more processors, individually or in combination, are further configured to:

determine whether the second logical address range indicated in the second command for the different operation at least partially overlaps with the first logical address range indicated in the first command for the fused operation, and

in response to determining that the second logical address range and the first logical address range at least partially overlap, abort the fused operation.

11. The storage device of claim 9 , wherein the data structure is a linked list, the memory includes a plurality of linked lists including the linked list, and each of the linked lists is associated with a different submission queue.

12. The storage device of claim 11 , wherein the one or more processors, individually or in combination, are further configured to:

report to a host device an indication that the storage device supports a smaller number of fused operation commands than a maximum number of the data structures in the memory, wherein the data structures are the linked lists.

13. The storage device of claim 12 , wherein the one or more processors, individually or in combination, are further configured to:

determine that a current number of stored fused operation commands is equal to the smaller number of fused operation commands, and

in response to a fused operation command in one of the linked lists including an earlier timestamp than the first command, replace the fused operation command with the first command in the one of the linked lists.

14. The storage device of claim 9 , wherein the data structure is a linked list, and wherein the one or more processors, individually or in combination, are further configured to:

from a time when the first command is received from the submission queue until a time when the first command is stored in the linked list, prevent reception of subsequent commands including an overlapping logical address range with the first command.

15. A storage device, comprising:

a memory including a plurality of data structures, wherein each of the data structures is associated with a different submission queue; and

one or more processors coupled to the memory, the one or more processors, individually or in combination, configured to:

receive a first command for a fused operation from one of the different submission queues, the first command indicating a first logical address range,

store the first command in one of the data structures,

receive a second command for the fused operation from the one of the different submission queues, the second command indicating a second logical address range,

determine whether the second command corresponds to the fused operation and whether the first logical address range is same as the second logical address range,

store the second command in the one of the data structures in response to determining that the second command corresponds to the fused operation and that the first logical address range is the same as the second logical address range, and

perform the fused operation in response to storing the second command.

16. The storage device of claim 15 , wherein the one or more processors, individually or in combination, are further configured to:

prior to receiving the second command, receive a third command for a different operation from the one of the different submission queues,

determine whether the third command corresponds to the fused operation, and

in response to a determination that the third command does not correspond to the fused operation, perform the different operation prior to the fused operation.

17. The storage device of claim 15 , wherein the one or more processors, individually or in combination, are further configured to:

from a time when the first command is received from the one of the different submission queues until a time when the first command is stored in the data structure, prevent reception of subsequent commands including an overlapping logical address range with the first command.

18. The storage device of claim 15 , wherein the first command is a compare command and the second command is a write command.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2022
From: JAIN, RAHUL; V M, ARVIND KUMAR
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060578/0157 →