IP Library Granted Patent US 9,564,581
Granted Patent B1
US 9,564,581 · App. 14/948,145 · Granted Feb 7, 2017

Magnetoresistive effect devices having enhanced magnetic anisotropy

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Quick Facts
Patent No.
US 9,564,581
App. No.
14/948,145
Granted
Feb 7, 2017
Kind
B1
Abstract

Embodiments of the present disclosure generally relate to memory devices having enhanced perpendicular magnetic anisotropy. The memory device includes a plurality of first leads, a plurality of second leads, and a plurality of memory cells having a plurality of magnetic layers and a tunneling barrier layer. An interfacial layer is incorporated in each memory cell between one of the magnetic layers and the tunneling barrier layer to enhance perpendicular magnetic anisotropy, while preserving high tunneling magnetoresistance.

Claims (43)

1. A memory cell, comprising:

a first magnetic layer;

a tunneling barrier layer;

a second magnetic layer; and

at least a first interfacial layer disposed on and in contact with the tunneling barrier layer, wherein the first interfacial layer comprises MgAl 2 O 4 or a non-stoichiometric MgAl x O y where the oxygen content is slightly less than that found in the stoichiometric MgAl 2 O 4 .

2. The memory cell of claim 1 , wherein the first interfacial layer is disposed on and in contact with the first magnetic layer.

3. The memory cell of claim 1 , wherein the first interfacial layer is disposed on and in contact with the second magnetic layer.

4. The memory cell of claim 1 , wherein the first interfacial layer has a thickness of about 1 to about 5 atomic layers.

5. The memory cell of claim 1 , further comprising a second interfacial layer disposed on and in contact with the tunneling barrier layer.

6. A memory device, comprising:

a plurality of first leads;

a plurality of second leads; and

a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads, wherein each memory cell of the plurality of memory cells, comprises:

a first magnetic layer;

a tunneling barrier layer;

a second magnetic layer; and

at least a first interfacial layer disposed on and in contact with the tunneling barrier layer, wherein the first interfacial layer comprises MgAl 2 O 4 or a non-stoichiometric MgAl x O y where the oxygen content is slightly less than that found in the stoichiometric MgAl 2 O 4 .

7. The memory device of claim 6 , wherein the first interfacial layer is disposed on and in contact with the first magnetic layer.

8. The memory device of claim 6 , wherein the first interfacial layer is disposed on and in contact with the second magnetic layer.

9. The memory device of claim 6 , wherein the first interfacial layer has a thickness of about 1 to about 5 atomic layers.

10. The memory device of claim 6 , further comprising a second interfacial layer disposed on and in contact with the tunneling barrier layer.

11. The memory device of claim 10 , wherein the first interfacial layer is disposed on and in contact with the first magnetic layer and the second interfacial layer is disposed on and in contact with the second magnetic layer.

12. A memory device, comprising:

a plurality of first leads;

a plurality of second leads; and

a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads, wherein each memory cell of the plurality of memory cells, comprises:

a first magnetic layer;

a tunneling barrier layer;

a second magnetic layer;

at least a first interfacial layer disposed on and in contact with the tunneling barrier layer; and

a second interfacial layer disposed on and in contact with the tunneling barrier layer, wherein the first interfacial layer is disposed on and in contact with the first magnetic layer and the second interfacial layer is disposed on and in contact with the second magnetic layer, wherein the first and second interfacial layers comprise MgAl 2 O 4 .

13. A memory device, comprising:

a plurality of first leads;

a plurality of second leads; and

a plurality of memory cells disposed between the plurality of first leads and the plurality of second leads, wherein each memory cell of the plurality of memory cells, comprises:

a first ferromagnetic layer;

an oxide barrier layer;

a second ferromagnetic layer;

a first interfacial layer comprising MgAl 2 O 4 disposed on and in contact with the first ferromagnetic layer and the oxide barrier layer; and

a second interfacial layer comprising MgAl 2 O 4 disposed on and in contact with the second ferromagnetic layer and the oxide barrier layer.

14. The memory device of claim 13 , wherein the plurality of first leads are disposed over the plurality of second leads, and the plurality of first leads are perpendicular to the plurality of second leads.

15. The memory device of claim 14 , wherein each memory cell of the plurality of memory cells is coupled to a lead of the plurality of first leads and a lead of the plurality of second leads.

16. The memory device of claim 15 , wherein the first ferromagnetic layer is disposed on and in contact with a lead of the plurality of first leads and the second ferromagnetic layer is disposed on and in contact with a lead of the plurality of second leads.

Assignments (10)
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT SERIAL NO 15/025,946 PREVIOUSLY RECORDED AT REEL: 040831 FRAME: 0265. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 15, 2017
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 043973/0762 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 6, 2016
From: HGST NETHERLANDS B.V.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 040831/0265 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE ADDRESS PREVIOUSLY RECORDED AT REEL: 037117 FRAME: 0018. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Aug 11, 2016
From: CHOI, YOUNG-SUK; RUBIN, KURT ALLAN; STEWART, DEREK
To: HGST NETHERLANDS B.V.
Reel/Frame 039651/0839 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 23, 2015
From: CHOI, YOUNG-SUK; RUBIN, KURT ALLAN; STEWART, DEREK
To: HGST NETHERLANDS B.V.
Reel/Frame 037117/0018 →