Managing memory systems containing components with asymmetric characteristics
View Patent ↗A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.
1. A method of managing data that is stored in a storage system, the method comprising:
identifying, within a storage system, a first disruption region;
identifying, within the storage system, a second disruption region that is separate from the first disruption region;
associating portions of the first disruption region with portions of the second disruption region, where a first portion of the first disruption region is associated with a first portion of the second disruption region and a second portion of the first disruption region is associated with a second portion of the second disruption region;
receiving a first update to be written to the storage system; and
based on receipt of the first update to be written to the storage system:
writing the first update to the second portion of the second disruption region;
disabling read access to the first portion of the second disruption region during a first time period associated with writing the first update to the second portion to the second disruption region;
enabling data to be read from the first portion of the first disruption region during the first time period associated with writing the first update to the second portion to the second disruption region;
writing the first update to the second portion of the first disruption region;
disabling read access to the first portion of the first disruption region during a second time period associated with writing the first update to the second portion to the first disruption region; and
enabling data to be read from the first portion of the second disruption region during the second time period associated with writing the first update to the second portion to the first disruption region.
2. The method of claim 1 , wherein the second portion in the second disruption region is unutilized prior to writing the first update.
3. The method of claim 1 , wherein the second disruption region includes a previous instance of mirrored content prior to writing the first update to the second disruption region.
4. The method of claim 1 , wherein the first disruption region is in use when the first update is received.
5. The method of claim 1 , wherein the first portion and the second portion in the first disruption region are sequentially arranged.
6. The method of claim 1 , wherein the first portion and the second portion in the second disruption region are sequentially arranged.
7. The method of claim 1 , wherein the second portion in the first disruption region uses an identical offset for a memory controller-specified physical address offset as the second portion in the second disruption region.
8. The method of claim 1 , further comprising enabling a memory controller to read the first update from the second disruption region after the first update has been written to the second portion of the second disruption region.
9. The method of claim 1 , further comprising enabling a memory controller to read the first portion and the second portion from the second disruption region after the first update has been written to the second portion of the second disruption region.
10. The method of claim 1 , further comprising preserving data in the first portion of the second disruption region during the writing of the first update to the second portion of the second disruption region.
11. The method of claim 1 , further comprising using a memory controller configured to associate a memory management unit-specified physical address from a CPU with a first memory controller-specified physical address for the first disruption region and a second memory controller-specified physical address for the second disruption region.
12. The method of claim 1 , further comprising using an identical subaddress for the first portion in the first disruption region and the first portion in the second disruption region.
13. A system comprising:
a storage system that has multiple disruption regions including at least a first disruption region of the storage system that is separate from a second disruption region of the storage system; and
a controller configured to perform operations comprising:
identifying, within the storage system, the first disruption region;
identifying, within the storage system, the second disruption region that is separate from the first disruption region;
associating portions of the first disruption region with portions of the second disruption region, where a first portion of the first disruption region is associated with a first portion of the second disruption region and a second portion of the first disruption region is associated with a second portion of the second disruption region;
receiving a first update to be written to the storage system; and
based on receipt of the first update to be written to the storage system:
writing the first update to the second portion of the second disruption region;
disabling read access to the first portion of the second disruption region during a first time period associated with writing the first update to the second portion to the second disruption region;
enabling data to be read from the first portion of the first disruption region during the first time period associated with writing the first update to the second portion to the second disruption region;
writing the first update to the second portion of the first disruption region;
disabling read access to the first portion of the first disruption region during a second time period associated with writing the first update to the second portion to the first disruption region; and
enabling data to be read from the first portion of the second disruption region during the second time period associated with writing the first update to the second portion to the first disruption region.
14. The system of claim 13 , wherein the second portion in the second disruption region is unutilized prior to writing the first update.
15. The system of claim 13 , wherein the second disruption region includes a previous instance of mirrored content prior to writing the first update to the second disruption region.
16. The system of claim 13 , wherein the first disruption region is in use when the first update is received.
17. The system of claim 13 , wherein the first portion and the second portion in the first disruption region are sequentially arranged.
18. The system of claim 13 , wherein the first portion and the second portion in the second disruption region are sequentially arranged.
19. The system of claim 13 , wherein the second portion in the first disruption region uses an identical offset for a memory controller-specified physical address offset as the second portion in the second disruption region.
20. The system of claim 13 , wherein the operations further comprise enabling a memory controller to read the first update from the second disruption region after the first update has been written to the second portion of the second disruption region.