IP Library › Granted Patent US 11,456,754

Granted Patent B2

US 11,456,754 · App. 17/177,940 · Granted Sep 27, 2022

Fixed size soft bit lossy compression in flash memory

Inventors: Ran Zamir (Ramat Gan, IL); Eran Sharon (Rishon Lezion, IL); Idan Alrod (Herzeliya, IL); Alexander Bazarsky (Holon, IL); Yan Li (Milpitas, CA); A Harihara Sravan (Bangalore, IN)

Assignee: Western Digital Technologies, Inc.

H03M7/3062 G06F11/008 G06F12/08 H03M7/3064 G06F2212/401 G11C11/5671 G11C16/26

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Quick Facts

Patent No.: US 11,456,754
App. No.: 17/177,940
Granted: Sep 27, 2022
Kind: B2

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Abstract

A memory includes, in one embodiment, one or more storage elements; read/write circuitry; and compressed bit circuitry. The read/write circuitry is configured to read a set of hard bits from the one or more storage elements, and sense a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and the set of soft bits indicating a reliability of the set of hard bits. The compressed soft bit circuitry is configured to generate, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size, and output the fixed size compressed soft bits to a memory-to-controller bus.

Claims (106)

1. A memory, comprising:

one or more storage elements;

read/write circuitry configured to:

read a set of hard bits from the one or more storage elements, and

sense a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and each soft bit of the set of soft bits indicating a reliability of a corresponding hard bit of the set of hard bits; and

compressed soft bit circuitry configured to:

receive the set of soft bits,

generate, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size, and

output the fixed size compressed soft bits to a memory-to-controller bus.

2. The memory of claim 1 , wherein, to generate, with the fixed size soft bit lossy compression algorithm, the fixed size compressed soft bits by compressing the set of soft bits, the compressed soft bit circuitry is further configured to:

determine whether a first portion of the set of soft bits includes a first marked bit, a value and a location of the first marked bit indicating one hard bit in the set of hard bits is unreliable,

generate a first index that indicates the value and the location of the first marked bit in response to determining that the first portion includes the first marked bit,

determine whether a second portion of the set of soft bits includes a second marked bit, a value and a location of the second marked bit indicating a second hard bit in the set of hard bits is unreliable, and

generate a second index that indicates the value and the location of the second marked bit in response to determining that the second portion includes the second marked bit.

3. The memory of claim 2 , wherein, to generate the fixed size compressed soft bits by compressing the set of soft bits, the compressed soft bit circuitry is further configured to:

generate a third index that indicates there are no unreliable bits in the first portion in response to determining that the first portion does not include the first marked bit, and

generate a fourth index that indicates there are no unreliable bits in the second portion in response to determining that the second portion does not include the second marked bit.

4. The memory of claim 2 , wherein the first portion and the second portion each include all soft bits in the set of soft bits, and wherein a size of the first index and a size of the second index are equal to each other.

5. The memory of claim 2 , wherein the first portion and the second portion each includes less than all soft bits in the set of soft bits, and wherein a size of the first index and a size of the second index are equal to each other.

6. The memory of claim 2 , wherein the first portion and the second portion each includes less than all soft bits in the set of soft bits, and wherein a size of the first index and a size of the second index are not equal to each other.

7. The memory of claim 1 , wherein, to generate with the fixed size soft bit lossy compression algorithm, the fixed size compressed soft bits by compressing the set of soft bits, the compressed soft bit circuitry is further configured to:

determine whether a first portion of the set of soft bits includes one or more marked bits, a value and a location of each of the one or more marked bits indicating one hard bit in the set of hard bits is unreliable,

determine whether a second portion of the set of soft bits includes a second one or more marked bits, a value and a location of each of the second one or more marked bits indicating a corresponding a second hard bit in the set of hard bits is unreliable,

in response to determining that the first portion does not include the one or more marked bits and the second portion do not include the second one or more marked bits, generate a first index that indicates a first binary null value and a second index that indicates a second binary null value,

in response to determining that the first portion includes one of the one or more marked bits and the second portion does not include the second one or more marked bits, generate a third index that indicates a first binary value of the location of the one of the one or more marked bits and a fourth index that indicates a third binary null value,

in response to determining that the first portion does not include the one or more marked bits and the second portion includes one of the second one or more marked bits, generate a fifth index that indicates a fourth binary null value and a sixth index that indicates a second binary value of the location of the one of the second one or more marked bits,

in response to determining that the first portion includes the one of the one or more marked bits and the second portion includes the one of the second one or more marked bits, generate a seventh index that indicates a third binary value of the location of the one of the one or more marked bits and an eighth index that indicates a fourth binary value of the location of the one of the second one or more marked bits,

in response to determining that the first portion does not include the one or more marked bits and the second portion includes two of the second one or more marked bits, generate a ninth index that indicates a fifth binary value of the location of a first one of the second one or more marked bits and a tenth index that indicates a sixth binary value of the location of a second one of the second one or more marked bits, and

in response to determining that the first portion includes two of the one or more marked bits and the second portion does not include the second one or more marked bits, generate an eleventh index that indicates a seventh binary value of the location of a first one of the one or more marked bits and a twelfth index that indicates an eighth binary value of an offset of the location of a second one of the second one or more marked bits from the location of the first one of the one or more marked bits,

wherein the first portion and the second portion are each less than all soft bits in the set of soft bits.

8. The memory of claim 1 , wherein, to generate with the fixed size soft bit lossy compression algorithm, the fixed size compressed soft bits by compressing the set of soft bits, the compressed soft bit circuitry is further configured to:

determine whether one or more bytes of a first set of bytes of the set of soft bits includes one or more marked bits, a value and a location of each of the one or more marked bits indicating one hard bit in the set of hard bits is unreliable,

determine whether a second one or more bytes of a second set of bytes of the set of soft bits includes a second one or more marked bits, a value and a location of each of the second one or more marked bits indicating a second hard bit in the set of hard bits is unreliable,

in response to determining that the one or more bytes of the first set of bytes of the set of soft bits does not include the one or more marked bits and the second one or more bytes of the second set of bytes of the set of soft bits does not include the second one or more marked bits, generate the fixed size compressed soft bits with a first null binary value and a second null binary value,

in response to determining that the one or more bytes of the first set of bytes of the set of soft bits includes one of the one or more marked bits and the second one or more bytes of the second set of bytes of the set of soft bits does not include the second one or more marked bits, generate the fixed size compressed soft bits with a first binary value that indicates a first byte location of the one of the one or more marked bits and a third null binary value,

in response to determining that the one or more bytes of the first set of bytes of the set of soft bits does not include the one or more marked bits and the second one or more bytes of the second set of bytes of the set of soft bits includes one of the second one or more marked bits, generate the fixed size compressed soft bits with a fourth null binary value and a second binary value that indicates a second byte location of the one of the second one or more marked bits,

in response to determining that the one or more bytes of the first set of bytes of the set of soft bits includes one of the one or more marked bits and the second one or more bytes of the second set of bytes of the set of soft bits includes one of the second one or more marked bits, generate the fixed size compressed soft bits with a third binary value that indicates a third byte location of the one of the one or more marked bits and a fourth binary value that indicates a fourth byte location of the one of the second one or more marked bits,

in response to determining that the one or more bytes of the first set of bytes of the set of soft bits does not include the one or more marked bits and the second one or more bytes of the second set of bytes of the set of soft bits includes two of the second one or more marked bits, generate the fixed size compressed soft bits with a fifth null binary value and a fifth binary value that indicates a fifth byte location of a first one of the second one or more marked bits and a sixth byte location of a second one of the second one or more marked bits, and

in response to determining that the one or more bytes of the first set of bytes of the set of soft bits includes two of the one or more marked bits and the second one or more bytes of the second set of bytes of the set of soft bits does not include the second one or more marked bits, generate a sixth binary value that indicates a seventh byte location of a first one of the one or more marked bits and a seventh binary value that indicates an eighth byte location of a second one of the one or more marked bits that is an offset from the seventh byte location.

9. A method, comprising:

reading, with read/write circuitry, a set of hard bits from one or more storage elements;

sensing, with the read/write circuitry, a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and each soft bit of the set of soft bits indicating a reliability of a corresponding hard bit of the set of hard bits;

receiving, with compressed soft bit circuitry, the set of soft bits;

generating, with the compressed soft bit circuitry and a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size; and

outputting, with the compressed soft bit circuitry, the fixed size compressed soft bits to a memory-to-controller bus.

10. The method of claim 9 , wherein generating, with the compressed soft bit circuitry and the fixed size soft bit lossy compression algorithm, the fixed size compressed soft bits by compressing the set of soft bits further includes:

determining whether a first portion of the set of soft bits includes a first marked bit, a value and a location of the first marked bit indicating one hard bit in the set of hard bits is unreliable,

generating a first index that indicates the value and the location of the first marked bit in response to determining that the first portion includes the first marked bit,

determining whether a second portion of the set of soft bits includes a second marked bit, a value and a location of the second marked bit indicating a second hard bit in the set of hard bits is unreliable, and

generating a second index that indicates the value and the location of the second marked bit in response to determining that the second portion includes the second marked bit.

11. The method of claim 10 , wherein generating, with the compressed soft bit circuitry and the fixed size soft bit lossy compression algorithm, the fixed size compressed soft bits by compressing the set of soft bits further includes

generating a third index that indicates there are no unreliable bits in the first portion in response to determining that the first portion does not include the first marked bit, and

generating a fourth index that indicates there are no unreliable bits in the second portion in response to determining that the second portion does not include the second marked bit.

12. The method of claim 10 , wherein the first portion and the second portion each include all soft bits in the set of soft bits, and wherein a size of the first index and a size of the second index are equal to each other.

13. The method of claim 10 , wherein the first portion and the second portion each includes less than all soft bits in the set of soft bits, and wherein a size of the first index and a size of the second index are equal to each other.

14. The method of claim 10 , wherein the first portion and the second portion each includes less than all soft bits in the set of soft bits, and wherein a size of the first index and a size of the second index are not equal to each other.

15. The method of claim 9 , wherein generating, with the compressed soft bit circuitry and the fixed size soft bit lossy compression algorithm, the fixed size compressed soft bits by compressing the set of soft bits further includes:

determining whether a first portion of the set of soft bits includes one or more marked bits, a value and a location of each of the one or more marked bits indicating one hard bit in the set of hard bits is unreliable,

determining whether a second portion of the set of soft bits includes a second one or more marked bits, a value and a location of each of the second one or more marked bits indicating a corresponding second hard bit in the set of hard bits is unreliable,

in response to determining that the first portion includes one of the one or more marked bits and the second portion does not include the second one or more marked bits, generating a third index that indicates a first binary value of the location of the one of the one or more marked bits and a fourth index that indicates a third binary null value,

in response to determining that the first portion does not include the one or more marked bits and the second portion includes one of the second one or more marked bits, generating a fifth index that indicates a fourth binary null value and a sixth index that indicates a second binary value of the location of the one of the second one or more marked bits,

in response to determining that the first portion includes the one of the one or more marked bits and the second portion includes the one of the second one or more marked bits, generating a seventh index that indicates a third binary value of the location of the one of the one or more marked bits and an eighth index that indicates a fourth binary value of the location of the one of the second one or more marked bits,

in response to determining that the first portion does not include the one or more marked bits and the second portion includes two of the second one or more marked bits, generating a ninth index that indicates a fifth binary value of the location of a first one of the second one or more marked bits and a tenth index that indicates a sixth binary value of the location of a second one of the second one or more marked bits, and

in response to determining that the first portion includes two of the one or more marked bits and the second portion does not include the second one or more marked bits, generating an eleventh index that indicates a seventh binary value of the location of a first one of the one or more marked bits and a twelfth index that indicates an eighth binary value of an offset of the location of a second one of the second one or more marked bits from the location of the first one of the one or more marked bits,

wherein the first portion and the second portion are each less than all soft bits in the set of soft bits.

16. The method of claim 9 , wherein generating, with the compressed soft bit circuitry and the fixed size soft bit lossy compression algorithm, the fixed size compressed soft bits by compressing the set of soft bits further includes:

determining whether one or more bytes of a first set of bytes of the set of soft bits includes one or more marked bits, a value and a location of each of the one or more marked bits indicating one hard bit in the set of hard bits is unreliable,

determining whether a second one or more bytes of a second set of bytes of the set of soft bits includes a second one or more marked bits, a value and a location of each of the second one or more marked bits indicating a second hard bit in the set of hard bits is unreliable,

in response to determining that the one or more bytes of the first set of bytes of the set of soft bits does not include the one or more marked bits and the second one or more bytes of the second set of bytes of the set of soft bits includes one of the second one or more marked bits, generate the fixed size compressed soft bits with a fourth null binary value and a second binary value that indicates a second byte location of the one of the second one or more marked bits,

in response to determining that the one or more bytes of the first set of bytes of the set of soft bits includes one of the one or more marked bits and the second one or more bytes of the second set of bytes of the set of soft bits includes one of the second one or more marked bits, generate the fixed size compressed soft bits with a third binary value that indicates a third byte location of the one of the one or more marked bits and a fourth binary value that indicates a fourth byte location of the one of the second one or more marked bits,

in response to determining that the one or more bytes of the first set of bytes of the set of soft bits does not include the one or more marked bits and the second one or more bytes of the second set of bytes of the set of soft bits includes two of the second one or more marked bits, generate the fixed size compressed soft bits with a fifth null binary value and a fifth binary value that indicates a fifth byte location of a first one of the second one or more marked bits and a sixth byte location of a second one of the second one or more marked bits, and

17. An apparatus, comprising:

means for reading a set of hard bits from one or more storage elements;

means for sensing a first set of soft bits while reading the set of hard bits from the one or more storage elements, the first set of soft bits having a first fixed size, and each soft bit of the first set of soft bits indicating a reliability of a corresponding hard bit of the set of hard bits;

means for generating, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the first set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size;

means for decompressing the fixed size compressed soft bits to determine a second set of soft bits; and

means for decoding read data with the second set of soft bits,

wherein the second set of soft bits is different than the first set of soft bits.

18. The apparatus of claim 17 , wherein means for generating, with the fixed size soft bit lossy compression algorithm, the fixed size compressed soft bits by compressing the first set of soft bits further includes

means for determining whether a first portion of the first set of soft bits includes a first marked bit, a value and a location of the first marked bit indicating one hard bit in the set of hard bits is unreliable;

means for generating a first index that indicates the value and the location of the first marked bit in response to determining that the first portion includes the first marked bit;

means for determining whether a second portion of the first set of soft bits includes a second marked bit, a value and a location of the second marked bit indicating a second hard bit in the set of hard bits is unreliable; and

means for generating a second index that indicates the value and the location of the second marked bit in response to determining that the second portion includes the second marked bit.

19. The apparatus of claim 17 , wherein means for generating, with the fixed size soft bit lossy compression algorithm, the fixed size compressed soft bits by compressing the first set of soft bits further includes

means for determining whether a first portion of the first set of soft bits includes one or more marked bits, a value and a location of each of the one or more marked bits indicating one hard bit in the set of hard bits is unreliable;

means for determining whether a second portion of the first set of soft bits includes a second one or more marked bits, a value and a location of each of the second one or more marked bits indicating a corresponding second hard bit in the set of hard bits is unreliable;

in response to determining that the first portion and the second portion do not include the second one or more marked bits, means for generating a first index that indicates a first binary null value and a second index that indicates a second binary null value;

in response to determining that the first portion includes one of the one or more marked bits and the second portion does not include the second one or more marked bits, means for generating a third index that indicates a first binary value of the location of the one of the one or more marked bits and a fourth index that indicates a third binary null value;

in response to determining that the first portion does not include the one or more marked bits and the second portion includes one of the second one or more marked bits, means for generating a fifth index that indicates a fourth binary null value and a sixth index that indicates a second binary value of the location of the one of the second one or more marked bits;

in response to determining that the first portion includes the one of the one or more marked bits and the second portion includes the one of the second one or more marked bits, means for generating a seventh index that indicates a third binary value of the location of the one of the one or more marked bits and an eighth index that indicates a fourth binary value of the location of the one of the second one or more marked bits;

in response to determining that the first portion does not include the one or more marked bits and the second portion includes two of the second one or more marked bits, means for generating a ninth index that indicates a fifth binary value of the location of a first one of the second one or more marked bits and a tenth index that indicates a sixth binary value of the location of a second one of the second one or more marked bits; and

in response to determining that the first portion includes two of the one or more marked bits and the second portion does not include the second one or more marked bits, means for generating an eleventh index that indicates a seventh binary value of the location of a first one of the one or more marked bits and a twelfth index that indicates an eighth binary value of an offset of the location of a second one of the second one or more marked bits from the location of the first one of the one or more marked bits,

wherein the first portion and the second portion are each less than all soft bits in the first set of soft bits.

20. The apparatus of claim 17 , wherein means for generating, with the fixed size soft bit lossy compression algorithm, the fixed size compressed soft bits by compressing the first set of soft bits further includes

means for determining whether one or more bytes of a first set of bytes of the first set of soft bits includes one or more marked bits, a value and a location of each of the one or more marked bits indicating one hard bit in the set of hard bits is unreliable;

means for determining whether a second one or more bytes of a second set of bytes of the first set of soft bits includes a second one or more marked bits, a value and a location of each of the second one or more marked bits indicating a second hard bit in the set of hard bits is unreliable;

in response to determining that the one or more bytes of the first set of bytes of the first set of soft bits does not include the one or more marked bits and the second one or more bytes of the second set of bytes of the first set of soft bits does not include the second one or more marked bits, means for generating the fixed size compressed soft bits with a first null binary value and a second null binary value;

in response to determining that the one or more bytes of the first set of bytes of the first set of soft bits includes one of the one or more marked bits and the second one or more bytes of the second set of bytes of the first set of soft bits does not include the second one or more marked bits, means for generating the fixed size compressed soft bits with a first binary value that indicates a first byte location of the one of the one or more marked bits and a third null binary value;

in response to determining that the one or more bytes of the first set of bytes of the first set of soft bits does not include the one or more marked bits and the second one or more bytes of the second set of bytes of the first set of soft bits includes one of the second one or more marked bits, means for generating the fixed size compressed soft bits with a fourth null binary value and a second binary value that indicates a second byte location of the one of the second one or more marked bits,

in response to determining that the one or more bytes of the first set of bytes of the first set of soft bits includes one of the one or more marked bits and the second one or more bytes of the second set of bytes of the first set of soft bits includes one of the second one or more marked bits, means for generating the fixed size compressed soft bits with a third binary value that indicates a third byte location of the one of the one or more marked bits and a fourth binary value that indicates a fourth byte location of the one of the second one or more marked bits;

in response to determining that the one or more bytes of the first set of bytes of the first set of soft bits does not include the one or more marked bits and the second one or more bytes of the second set of bytes of the first set of soft bits includes two of the second one or more marked bits, means for generating the fixed size compressed soft bits with a fifth null binary value and a fifth binary value that indicates a fifth byte location of a first one of the second one or more marked bits and a sixth byte location of a second one of the second one or more marked bits; and

in response to determining that the one or more bytes of the first set of bytes of the first set of soft bits includes two of the one or more marked bits and the second one or more bytes of the second set of bytes of the first set of soft bits does not include the second one or more marked bits, means for generating a sixth binary value that indicates a seventh byte location of a first one of the one or more marked bits and a seventh binary value that indicates an eighth byte location of a second one of the one or more marked bits that is an offset from the seventh byte location.

Assignments (10)

PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025

From: JPMORGAN CHASE BANK, N.A., AS AGENT

To: SANDISK TECHNOLOGIES, INC.

Reel/Frame 071382/0001 →

SECURITY AGREEMENT Recorded Apr 25, 2025

From: SANDISK TECHNOLOGIES, INC.

To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT

Reel/Frame 071050/0001 →

PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024

From: SANDISK TECHNOLOGIES, INC.

To: JPMORGAN CHASE BANK, N.A., AS THE AGENT