IP Library Granted Patent US 11,487,544
Granted Patent B2
US 11,487,544 · App. 16/744,059 · Granted Nov 1, 2022

Method and device for simultaneously decoding data in parallel to improve quality of service

Inventors: Shay Benisty (Beer Sheva, IL); Eran Banani (Meitar, IL); Yuri Ryabinin (Beer Sheva, IL)
Assignee: Western Digital Technologies, Inc.
G06F9/3822G06F9/30196G06F9/3836G06F9/546G06F12/0246
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Quick Facts
Patent No.
US 11,487,544
App. No.
16/744,059
Granted
Nov 1, 2022
Kind
B2
Abstract

The present disclosure generally relates to a method and device for simultaneously decoding data. Rather than sending data to be decoded to a single decoder, the data can be sent to multiple, available decoders so that the data can be decode in parallel. The data decoded from the first decoder that completes decoding of the data will be delivered to the host device. All remaining decoded data that was decoded in parallel will be discarded. The decoders operating simultaneously in parallel can operate using different parameters such as different calculation precision (power levels). By utilizing multiple decoders simultaneously in parallel, the full functionality of the data storage device's decoding capabilities are utilized without increasing latency.

Claims (39)

1. A data storage device, comprising:

a plurality of nonvolatile memory devices;

a plurality of decoders, wherein the plurality of decoders is equal in number to the plurality of nonvolatile memory devices;

a scheduler coupled to the plurality of decoders; and

a controller coupled to the plurality of nonvolatile memory devices, the scheduler, and the plurality of decoders, wherein the controller is configured to do the following when operating in low queue depth mode:

receive a read request from a host device to retrieve data from the plurality of nonvolatile memory devices;

retrieve the data from at least one nonvolatile memory device of the plurality of nonvolatile memory devices;

decode the data in parallel in at least two decoders of the plurality of decoders[H] wherein the at least two decoders have at least one different parameter; and

deliver the decoded data to the host device.

2. The data storage device of claim 1 , wherein the controller is configured to determine whether the plurality of decoders operated in a low queue depth mode immediately prior to receiving the read request.

3. The data storage device of claim 1 , wherein the controller is configured to receive the decoded data from the at least two decoders.

4. The data storage device of claim 3 , wherein the controller is configured to deliver the decoded data to the host device from a first decoder of the at least two decoders which was decoded first.

5. The data storage device of claim 4 , wherein the controller is configured to discard any decoded data from a decoder of the at least two decoders operating in parallel that did not finish decoding the data before the first decoder of the at least two decoders.

6. The data storage device of claim 1 , wherein at least one decoder operates at a different calculation precision, power level, and/or different configuration than another decoder.

7. The data storage device of claim 1 , further comprising an arbiter coupled to the plurality of decoders.

8. The data storage device of claim 1 , further comprising a plurality of flash interface modules, wherein one flash interface module of the plurality of flash interface modules is disposed between one decoder of the plurality of decoders and a corresponding nonvolatile memory device of the plurality of nonvolatile memory devices.

9. A data storage device, comprising:

at least one nonvolatile memory device;

a pool of decoders comprising a plurality of decoders, wherein each decoder of the plurality of decoders operates at a different calculation precision, power level, and/or different configuration;

a scheduler coupled to the pool of decoders, wherein the scheduler is configured to direct read data from the at least one nonvolatile memory device to the pool of decoders; and

a controller coupled to the at least one nonvolatile memory device, the pool of decoders, and the scheduler, wherein the controller is configured to do the following when operating in either high queue depth mode or low queue depth mode:

receive a read request from a host device to retrieve read data from the at least one nonvolatile memory device;

retrieve the read data from at least one nonvolatile memory device;

decode the read data in at least two decoders operating in parallel of the pool of decoders, wherein the at least two decodes operate with at least one different parameter for decoding; and

deliver the decoded data to the host device.

10. The data storage device of claim 9 , wherein the controller is configured to determine which decoders are available to receive the read data to decode.

11. The data storage device of claim 10 , wherein the controller is configured to determine which of the available decoders operated in a low queue depth mode immediately prior to receiving the read request.

12. The data storage device of claim 9 , wherein at least one decoder operates in a low power mode and at least one decoder operates in a full power mode.

13. The data storage device of claim 9 , further comprising a single flash interface module coupled between the pool of decoders and the at least one nonvolatile memory device.

14. The data storage device of claim 9 , wherein the at least two decoders operating in parallel of the pool of decoders operate in full power mode, and wherein the at least two decoders have different decoding settings.

15. The data storage device of claim 9 , wherein an initial log likelihood ratio (LLR) table is used by at least one decoder operating in lower power mode and by at least one decoder operating in full power mode.

16. The data storage device of claim 9 , wherein a maximum number of iterations for two different decoders operating in lower power mode is configured differently.

17. A data storage device, comprising:

at least one nonvolatile memory device;

means to decode the same data multiple times simultaneously with at least one different parameter for decoding in each instance, wherein the means to decode is coupled to the at least one nonvolatile memory device; and

means to deliver decoded data to a host device, wherein the means to deliver is coupled to the means to decode.

18. The data storage device of claim 17 , further comprising means to schedule operation of the means to decode, wherein the means to schedule is coupled to the means to decode.

19. The data storage device of claim 17 , wherein a plurality of nonvolatile memory devices are coupled to a single means to decode.

20. The data storage device of claim 17 , further comprising an arbiter coupled to the means to deliver.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052025 FRAME 0088 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058965/0699 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2020
From: BENISTY, SHAY; BANANI, ERAN; RYABININ, YURI
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052192/0308 →
SECURITY INTEREST Recorded Feb 26, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052025/0088 →