Semiconductor device including optional pad interconnect
A semiconductor device is disclosed including semiconductor die formed with functionally redundant main and optional die bond pads. In examples, the optional die bond pad is configured to be optionally redundant to the main die bond pad by forming the optional die bond pad with first and second electrically isolated portions, and electrically interconnecting the main die bond pad with the first portion of the second die bond pad. The second die bond pad may or may not be made redundant to the first die bond pad depending on whether an electrically conductive material is deposited on the first and second portions of the optional die bond pad.
1. A semiconductor die, comprising:
a plurality a die bond pads, comprising:
a first die bond pad, and
a second die bond pad configured to provide functional redundancy to the first die bond pad; and
a metal interconnect having a first end connected to the first die bond pad and a second end, opposite the first end, connected to at least a portion of the second die bond pad.
2. The semiconductor die of claim 1 , wherein the second die bond pad comprises a first portion, and a second portion electrically isolated from the first portion.
3. The semiconductor die of claim 2 , wherein the first die bond pad is electrically coupled to the first portion of the second die bond pad.
4. The semiconductor die of claim 1 , wherein the second die bond pad has a single uniform surface layer.
5. The semiconductor die of claim 1 , wherein the first and second die bond pads are adjacent to each other along an edge of the semiconductor die.
6. A semiconductor die, comprising:
a first major surface;
a second major surface opposed to the first major surface;
integrated circuits formed adjacent the first major surface;
a plurality a die bond pads, the plurality of die bond pads comprising:
a first die bond pad electrically coupled to a first integrated circuit, and
a second die bond pad configured to optionally perform as a redundant die bond pad to the first die bond pad, the second die bond pad comprising:
a first portion electrically coupled to the first die bond pad, and
a second portion electrically isolated from the first portion, the second portion having a circular footprint and having an electrical lead extending therefrom, the first portion surrounding the second portion, with the exception that the first portion is electrically isolated from the electrical lead extending from the second portion.
7. The semiconductor die of claim 6 , wherein the second die bond pad performs as a redundant die bond pad to the first die bond pad upon electrically connecting the first and second portions of the second die bond pad.
8. The semiconductor die of claim 6 , wherein the second die bond pad does not perform as a redundant die bond pad to the first die bond pad where the first and second portions of the second die bond pad remain electrically isolated from each other.
9. The semiconductor die of claim 6 , further comprising a metal interconnect extending between the first die bond pad and the first portion of the second die bond pad for electrically coupling the first die bond pad to the first portion of the second die bond pad.
10. The semiconductor die of claim 9 , wherein the metal interconnect is formed of the same material and at a same level relative to the first major surface of the semiconductor die as the first and second die bond pads.
11. The semiconductor die of claim 9 , wherein the metal interconnect is formed at a level that is further away from the first major surface of the semiconductor die than the first and second die bond pads.
12. The semiconductor die of claim 9 , wherein the metal interconnect is formed from a redistribution layer.
13. The semiconductor die of claim 6 , wherein the semiconductor die is a NAND flash memory semiconductor die.
14. A semiconductor device, comprising:
a substrate;
a plurality of stacked semiconductor die mounted to the substrate, a semiconductor die of the stacked semiconductor die comprising:
a first die bond pad,
a second die bond pad configured to optionally perform as a redundant die bond pad to the first die bond pad, and
an electrically conductive material, wherein the second die bond pad is configured to perform as the redundant die bond pad to the first die bond pad upon the electrically conductive material being applied over a surface of the second die bond pad.
15. The semiconductor device of claim 14 , the second die bond pad comprising:
a first portion electrically coupled to the first die bond pad, and
a second portion separated from the first portion by a gap.
16. The semiconductor device of claim 15 , wherein the second die bond pad is configured to perform as the redundant die bond pad to the first die bond pad upon the electrically conductive material being applied over the first and second portions of the second die bond pad.
17. The semiconductor device of claim 14 , wherein the electrically conductive material is a ball bump deposited on the second die bond pad.
18. The semiconductor device of claim 14 , wherein the electrically conductive material is one of solder paste, a solder ball and a solder bump.
19. The semiconductor device of claim 14 , further comprising a plurality of wire bonds and ball bumps electrically interconnecting the plurality of semiconductor die and the substrate, the electrically conductive material comprising a ball bump of the plurality of ball bumps.
20. A method of fabricating a semiconductor device with a pair of die bond pads on a semiconductor die that are optionally redundant to each other, comprising the steps of:
(a) forming a first die bond pad of the pair of die bond pads on the semiconductor die;
(b) forming a second die bond pad of the pair of die bond pads with electrically isolated first and second portions on the semiconductor die; and
(c) electrically coupling the first die bond pad with the first portion of the second die bond pad.
21. The method of claim 20 , further comprising the step of making the second die bond pad redundant to the first die bond pad by depositing an electrically conductive material over the first and second portions of the second die bond pad.
22. The method of claim 20 , further comprising the step of forming wire bonds and ball bumps on die bond pads of the semiconductor die to electrically connect the semiconductor die within the semiconductor device.
23. The method of claim 22 , wherein said step of forming wire bonds and ball bumps comprises the step of making the second die bond pad redundant to the first die bond pad by depositing a ball bump over the first and second portions of the second die bond pad.
24. The method of claim 20 , wherein said step of electrically coupling the first die bond pad with the first portion of the second die bond pad comprises the step of forming a metal interconnect between the first die bond pad and the first portion of the second die bond pad.
25. The method of claim 24 , wherein said step of forming the metal interconnect comprises the step of forming the metal interconnect in the same process in which the first and second die bond pads are formed.
26. The method of claim 24 , wherein said step of forming the metal interconnect comprises the step of forming the metal interconnect before the first and second die bond pads are formed.
27. The method of claim 24 , wherein said step of forming the metal interconnect comprises the step of forming the metal interconnect as a redistribution layer.
28. A semiconductor die formed from a semiconductor wafer, the semiconductor die comprising:
a first major surface;
a second major surface opposed to the first major surface;
integrated circuits formed adjacent the first major surface;
a first pad means for receiving a first ball bump, and
a second pad means for optionally performing as a redundant die bond pad to the first pad means.
29. The semiconductor die of claim 28 , further comprising a metal interconnect for electrically interconnecting the first pad means with a portion of the second pad means.