IP Library Granted Patent US 11,282,580
Granted Patent B2
US 11,282,580 · App. 16/887,747 · Granted Mar 22, 2022

Data storage device with foggy-fine program sequence for reducing neighbor wordline interference

Inventors: Mayank Gupta (Bangalore, IN); Phani Raghavendra Yasasvi Gangavarapu (Bangalore, IN); Arun Balakrishnan (Bangalore, IN)
Assignee: Western Digital Technologies, Inc.
G11C16/3427G06F3/0604G06F3/0659G06F3/0679G11C16/08G11C16/10G11C16/14G11C16/0483
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Quick Facts
Patent No.
US 11,282,580
App. No.
16/887,747
Granted
Mar 22, 2022
Kind
B2
Abstract

A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory having a plurality of wordlines. The controller circuit is configured to program, with foggy-fine programming, a first portion of the plurality of wordlines to store first program data, program, with the foggy-fine programming, one or more wordlines of the plurality of wordlines in a non-fine state, the one or more wordlines neighboring the first portion, and program, with the foggy-fine programming, a second portion of the plurality of wordlines to store second program data, the second portion neighboring the one or more wordlines.

Claims (39)

1. A memory controller, comprising:

a memory interface configured to interface with a memory having a plurality of wordlines; and

a controller circuit configured to:

program, with foggy-fine programming, a first portion of the plurality of wordlines to store first program data,

program, with the foggy-fine programming, one or more wordlines of the plurality of wordlines in a non-fine state, the one or more wordlines neighboring the first portion, and

program, with the foggy-fine programming, a second portion of the plurality of wordlines to store second program data that is distinct from the first program data, the second portion neighboring the one or more wordlines.

2. The memory controller of claim 1 , wherein, to program the one or more wordlines of the plurality of wordlines in the non-fine state, the controller circuit is further configured to maintain the one or more wordlines in an erase state.

3. The memory controller of claim 1 , wherein, to program the one or more wordlines of the plurality of wordlines in the non-fine state, the controller circuit is further configured to program the one or more wordlines in a foggy state.

4. The memory controller of claim 1 , wherein the controller circuit is further configured to program, with the foggy-fine programming, a second one or more wordlines of the plurality of wordlines in a second non-fine state, the second one or more wordlines neighboring the first portion and not neighboring the one or more wordlines.

5. The memory controller of claim 4 , wherein, to program the second one or more wordlines of the plurality of wordlines in the second non-fine state, the controller circuit is further configured to maintain the second one or more wordlines in an erase state.

6. The memory controller of claim 1 , wherein the one or more wordlines is a single wordline.

7. The memory controller of claim 1 , wherein to program, with the foggy-fine programming, the second portion of the plurality of wordlines to store the second program data, the controller circuit is configured to

program the one or more wordlines in a fine state, and

program the second portion of the plurality of wordlines to store the second program data in response to programming the one or more wordlines in the fine state.

8. A method, comprising:

programming, with a controller circuit and foggy-fine programming, a first portion of a plurality of wordlines to store first program data;

programming, with the controller circuit and the foggy-fine programming, one or more wordlines of the plurality of wordlines in a non-fine state, the one or more wordlines neighboring the first portion, and

programming, with the controller circuit and the foggy-fine programming, a second portion of the plurality of wordlines to store second program data that is distinct from the first program data, the second portion neighboring the one or more wordlines.

9. The method of claim 8 , wherein programming the one or more wordlines of the plurality of wordlines in the non-fine state further includes maintaining the one or more wordlines in an erase state.

10. The method of claim 8 , wherein programming the one or more wordlines of the plurality of wordlines in the non-fine state further includes programming the one or more wordlines in a foggy state.

11. The method of claim 8 , further comprising:

programming a second one or more wordlines of the plurality of wordlines in a second non-fine state, the second one or more wordlines neighboring the first portion and not neighboring the one or more wordlines.

12. The method of claim 11 , wherein programming the second one or more wordlines of the plurality of wordlines in the second non-fine state further includes maintaining the second one or more wordlines in an erase state.

13. The method of claim 8 , wherein the one or more wordlines is a single wordline.

14. The method of claim 8 , wherein to programming the second portion of the plurality of wordlines to store the second program data further includes:

programming the one or more wordlines in a fine state, and

programming the second portion of the plurality of wordlines to store the second program data in response to programming the one or more wordlines in the fine state.

15. An apparatus, comprising:

means for programming, with foggy-fine programming, a first portion of a plurality of wordlines to store first program data using foggy-fine programming;

means for programming, with the foggy-fine programming, one or more wordlines of the plurality of wordlines in a non-fine state, the one or more wordlines neighboring the first portion; and

means for programming, with the foggy-fine programming, a second portion of the plurality of wordlines to store second program data that is distinct from the first program data, the second portion neighboring the one or more wordlines.

16. The apparatus of claim 15 , wherein the means for programming the one or more wordlines of the plurality of wordlines in the non-fine state further includes means for maintaining the one or more wordlines in an erase state.

17. The apparatus of claim 15 , wherein the means for programming the one or more wordlines of the plurality of wordlines in the non-fine state further includes means for programming the one or more wordlines in a foggy state.

18. The apparatus of claim 15 , further comprising:

means for programming, with the foggy-fine programming, a second one or more wordlines of the plurality of wordlines in a second non-fine state, the second one or more wordlines neighboring the first portion and not neighboring the one or more wordlines.

19. The apparatus of claim 18 , wherein the means for programming the second one or more wordlines of the plurality of wordlines in the second non-fine state further includes means for maintaining the second one or more wordlines in an erase state.

20. The apparatus of claim 15 , wherein the means for programming the second portion of the plurality of wordlines to store the second program data further includes:

means for programming the one or more wordlines in a fine state, and

means for programming the second portion of the plurality of wordlines to store the second program data in response to programming the one or more wordlines in the fine state.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 2, 2020
From: GUPTA, MAYANK; GANGAVARAPU, PHANI RAGHAVENDRA YASASVI; BALAKRISHNAN, ARUN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052807/0681 →