IP Library Granted Patent US 11,960,394
Granted Patent B2
US 11,960,394 · App. 17/870,407 · Granted Apr 16, 2024

Creating and using delta L2P entries

Inventors: Amir Shaharabany (Kochav Yair, IL); Shay Vaza (Alfey Menashe, IL)
Assignee: Western Digital Technologies, Inc.
G06F12/0246G06F3/0608G06F3/0656G06F3/0673G06F12/0292G06F2212/401G06F2212/7201
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Quick Facts
Patent No.
US 11,960,394
App. No.
17/870,407
Granted
Apr 16, 2024
Kind
B2
Abstract

The present disclosure generally relates to more efficient use of a delta buffer. To Utilize the delta buffer, an efficiency can be gained by utilizing absolute delta entries and relative delta entries. The absolute delta entry will include the type of delta entry, the L2P table index, the L2P table offset, and the PBA. The relative delta entry will include the type of delta entry, the L2P table offset, and the PBA offset. The relative delta entry will utilize about half of the storage space of the absolute delta entry. The relative delta entry can be used after an absolute delta entry so long as the relative delta entry is for data stored in the same block as the previous delta entry. If data is stored in a different block, then the delta entry will be an absolute delta entry.

Claims (35)

1. A data storage device, comprising:

one or more memory devices; and

a controller coupled to the one or more memory devices, wherein the controller is configured to:

create an absolute delta entry, wherein the absolute delta entry comprises a first number of bits, a type of entry, a table part index, a first offset in the table, and a physical block address (PBA);

create a relative delta entry, wherein the relative delta entry comprises a second number of bits, type of entry, a second offset in the table, and a PBA offset, wherein the first number of bits is greater than the second number of bits; and

store the relative delta entry and absolute delta entry in a delta buffer table, wherein the first offset in the table and the second offset in the table comprise an equal number of bits, and wherein the PBA comprises a greater number of bits than the PBA offset.

2. The data storage device of claim 1 , wherein the controller is further configured to:

create a second relative delta entry, wherein the second relative delta entry comprises a third number of bits; and

store the second relative delta entry in the delta buffer table.

3. The data storage device of claim 2 , wherein the third number of bits is equal to the second number of bits.

4. The data storage device of claim 1 , wherein creating the absolute delta entry comprises:

set a delta entry type equal to absolute;

set a delta entry table part index equal to table part index; and

set a delta entry PBA equal to PBA.

5. The data storage device of claim 4 , wherein the controller is further configured to perform the following:

set delta entry type equal to relative; and

set delta entry PBA offset equal to PBA minus a last absolute entry PBA.

6. The data storage device of claim 5 , wherein the delta entry PBA offset comprises fewer bits than the delta entry PBA.

7. The data storage device of claim 5 , wherein the relative entry does not include a table part index.

8. The data storage device of claim 1 , wherein the controller includes a flash translation layer (FTL) module.

9. The data storage device of claim 1 , wherein the controller is further configured to:

decode a delta buffer entry; and

determine whether the decoded delta buffer entry is an absolute delta entry.

10. The data storage device of claim 9 , wherein the controller is further configured to calculate an offset from PBA.

11. The data storage device of claim 10 , wherein a delta buffer is present, wherein the delta buffer comprises a plurality of regions and wherein a first entry in any region of the delta buffer is an absolute entry.

12. The data storage device of claim 11 , wherein the delta buffer comprises at least 64 regions.

13. The data storage device of claim 12 , wherein an offset is determined by a number of flash management units (FMUs).

14. A data storage device, comprising:

one or more memory devices; and

a controller coupled to the one or more memory devices, wherein the controller is configured to:

create an absolute delta entry, wherein the absolute delta entry comprises a first number of bits, wherein the first number of bits is between 55 and 64 bits;

create a relative delta entry, wherein the relative delta entry comprises a second number of bits, wherein the first number of bits is greater than the second number of bits, wherein the second number of bits is between 28 and 32 bits; and

store the relative delta entry and absolute delta entry in a delta buffer table.

15. The data storage device of claim 14 , wherein the first number of bits is 64 bits.

16. The data storage device of claim 15 , wherein the second number of bits is 32 bits.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2022
From: SHAHARABANY, AMIR; VAZA, SHAY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060640/0785 →