IP Library Granted Patent US 9,270,296
Granted Patent B1
US 9,270,296 · App. 14/100,435 · Granted Feb 23, 2016

Method and system for soft decoding through single read

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,270,296
App. No.
14/100,435
Granted
Feb 23, 2016
Kind
B1
Abstract

Systems and methods are disclosed for decoding solid-state memory cells using one-read soft decision decoding. A controller of a data storage device is configured to perform a first decoding of a first code word based at least in part on data associated with a reading of the first code word, and to detect a decoding failure associated with the first decoding. The controller determines reliability information for decoding the first code word in response to the decoding failure based at least in part on data associated with a successful decoding of a second code word and performs a second decoding of the first code word based at least in part on the reliability information.

Claims (42)

1. A data storage device comprising:

a non-volatile memory array including a plurality of non-volatile solid-state memory elements configured to store a plurality of code words; and

a controller configured to:

perform a first decoding of a first code word based at least in part on data associated with a reading of the first code word;

detect a decoding failure associated with the first decoding;

determine bit flip count data associated with a successful decoding of a second code word stored on a same page in the non-volatile memory array as the first code word;

determine reliability information for decoding the first code word in response to the decoding failure, the determining based at least in part on the bit flip count data associated with the successful decoding of the second code word; and

perform a second decoding of the first code word based at least in part on the reliability information.

2. The data storage device of claim 1 , wherein the controller is further configured to determine the reliability information for decoding the first code word without performing an additional read of the first code word.

3. The data storage device of claim 1 , wherein the first decoding is a hard decoding.

4. The data storage device of claim 1 , wherein the controller is further configured to determine the bit flip count data associated with the successful decoding of the second code word based on a comparison of successfully decoded data and pre-decoding data.

5. The data storage device of claim 1 , wherein:

the bit flip count data comprises a 0-to-1 bit flip count and a 1-to-0 bit flip count, and

the controller is further configured to determine the reliability information by maximizing a reliability value associated with read 0's and minimizing a reliability value associated with read 1's when the 0-to-1 bit flip count is greater than the 1-to-0 bit flip count.

6. The data storage device of claim 1 , wherein:

the bit flip count data comprises a 0-to-1 bit flip count and a 1-to-0 bit flip count, and

the controller is further configured to determine the reliability information by maximizing a reliability value associated with read 1's and minimizing a reliability value associated with read 0's when the 1-to-0 bit flip count is greater than the 0-to-1 bit flip count.

7. The data storage device of claim 1 , wherein the controller is further configured to determine the reliability information by consulting a hash table associating reliability values with the bit flip count data.

8. The data storage device of claim 1 , wherein the controller is further configured to determine the reliability information by associating pre-assigned reliability information with the first code word.

9. The data storage device of claim 1 , wherein the controller is further configured to determine updated reliability information when the second decoding fails.

10. The data storage device of claim 1 , wherein the controller is further configured to generate updated reliability information based on one or more additional reads when the second decoding fails.

11. The data storage device of claim 1 , wherein the reliability information comprises log likelihood ratio (LLR) data, and wherein the controller is further configured to perform the second decoding at least in part by providing the LLR data to a low-density parity-check code (LDPC) decoder.

12. A method of decoding data in a data storage system, the method comprising:

performing a first decoding of a first code word based at least in part on data associated with a reading of the first code word;

detecting a decoding failure associated with the first decoding;

determining bit flip count data associated with a successful decoding of a second code word stored on a same page in the non-volatile memory array as the first code word;

determining reliability information for decoding the first code word in response to the decoding failure, said determining based at least in part on the bit flip count data associated with a successful decoding of the second code word; and

performing a second decoding of the first code word based at least in part on the reliability information.

13. The method of claim 12 , wherein said determining the reliability information for decoding the first code word is performed without performing an additional read of the first code word.

14. The method of claim 12 , wherein the first decoding is a hard decoding.

15. The method of claim 12 , wherein said determining the bit flip count data associated with the successful decoding of the second code word is based on a comparison of successfully decoded data and pre-decoding data.

16. The method of claim 12 , wherein:

the bit flip count data comprises a 0-to-1 bit flip count and a 1-to-0 bit flip count, and

said determining the reliability information comprises maximizing a reliability value associated with read 0's and minimizing a reliability value associated with read 1's when the 0-to-1 bit flip count is greater than the 1-to-0 bit flip count.

17. The method of claim 12 , wherein:

the bit flip count data comprises a 0-to-1 bit flip count and a 1-to-0 bit flip count, and

said determining the reliability information comprises maximizing a reliability value associated with read 1's and minimizing a reliability value associated with read 0's when the 1-to-0 bit flip count is greater than the 0-to-1 bit flip count.

18. The method of claim 12 , wherein said determining the reliability information comprises consulting a hash table associating reliability values with the bit flip count data.

19. The method of claim 12 , wherein said determining the reliability information comprises associating pre-assigned reliability information with the first code word.

20. The method of claim 12 , further comprising determining updated reliability information when the second decoding fails.

21. The method of claim 12 , further comprising generating updated reliability information based on one or more additional reads when the second decoding fails.

22. The method of claim 12 , wherein the reliability information comprises log likelihood ratio (LLR) data, and wherein performing the second decoding comprises providing the LLR data to a low-density parity-check code (LDPC) decoder.

Assignments (13)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2014
From: NEMATI ANARAKI, MAJID; COMETTI, ALDO G.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 032299/0325 →