Reduce command latency using block pre-erase
A system and apparatus for secure NVM format by pre-erase is disclosed. According to certain embodiments when an NVM does into idle mode, one or more free blocks are serially popped from a free block heap. The free block is then physically erased in an SLC mode, and then pushed to a pre-erase heap. The process is performed in both SLC and TLC partitions, in the TLC partition the block becomes hybrid SLC (HSLC). This process increases a program erase count (PEC) value of the block, maintaining device longevity. When there is a need to use a new block, it is popped from the pre-erase heap. In some cases where there is a need to use a TLC block instead of an HSLC block, an erase operation is used that converts the block from HSLC to TLC, and does not increase a PEC value for the block.
1. A data storage device, comprising:
a non-volatile memory (NVM) device; and
a controller coupled to the NVM device and configured to perform a method for block pre-erase, the method comprising:
responsive to the NVM device being in an idle state:
identifying a free block in a free block heap;
erasing data in the free block to create an erased block;
pushing the erased block to a pre-erase block heap;
receiving a secure NVM format command, wherein execution of the secure NVM format command is synchronized with a command sync flow, wherein the pre-erase block heap is stored in a control sync flash translation layer (FTL) log; and
skipping an erase operation for blocks listed in the pre-erase block heap.
2. The data storage device of claim 1 , wherein the method further comprises, responsive to an erase command received from a host, popping the erased block from the pre-erase block heap.
3. The data storage device of claim 2 , wherein erasing the data comprises a single layer cell (SLC) erase.
4. The data storage device of claim 3 , wherein erasing the data further comprises converting a triple-layer cell (TLC) to an SLC and performing the SLC erase.
5. The data storage device of claim 3 , the method further comprising maintaining the erased block in an erased state.
6. The data storage device of claim 5 , wherein the pre-erase block heap is stored in a flash translation layer (FTL) of the controller.
7. The data storage device of claim 6 , the method further comprising updating the pre-erase block heap upon popping the erased block from the pre-erase block heap responsive to a write command.
8. A controller for a data storage device, comprising:
a memory comprising computer-readable instructions; and
a processor coupled to the memory and configured to read the computer-readable instructions that cause the processor to:
erase data from a block of memory from an NVM device to generate an erased block:
push the erased block to a pre-erase block heap;
receive an erase command for a block of the NVM device;
responsive to receiving the erase command, pop the erased block from the pre-erase block heap;
receive a secure NVM format command, wherein execution of the secure NVM format command is synchronized with a command sync flow, wherein the pre-erase block heap is stored in a control sync flash translation layer (FTL) log; and
skip an erase operation for blocks listed in the pre-erase block heap.
9. The controller of claim 8 , wherein the computer-readable instructions further cause the processor to:
allocate the block of memory to a free-block heap; and
identify an idle state of the NVM device, and responsive to identification of the idle state of the NVM device, erasing data from the block of memory.
10. The controller of claim 9 , wherein the computer-readable instructions that causes the processor to erase data from the block of memory comprises a single layer cell (SLC) erase.
11. The controller of claim 10 , wherein the computer-readable instructions that cause the processor to erase data from the block of memory comprises converting a triple layer cell (TLC) to an SLC and performing the SLC erase.
12. The controller of claim 11 , wherein the computer-readable instructions further cause the processor to maintain the erased block in an erased state.
13. The controller of claim 12 , further comprising a flash translation layer (FTL), wherein the pre-erase block heap is stored in the FTL.
14. The controller of claim 13 , wherein the computer-readable instructions further cause the processor to update the pre-erase block heap upon popping the erased block from the pre-erase block heap, responsive to a write command.
15. A data storage device, comprising:
an NVM means; and
a controller configured to:
detect an idle state of the NVM means:
identify a free block in a free block heap;
erase data in the free block, thereby generating an erased block; and
push the erased block to a pre-erase block heap;
receive a secure NVM format command, wherein execution of the secure NVM format command is synchronized with a command sync flow, wherein the pre-erase block heap is stored in a control sync flash translation layer (FTL) log; and
skip an erase operation for blocks listed in the pre-erase block heap.
16. The data storage device of claim 15 , the controller being further configured to receive an erase command, and responsive to the erase command, pop the erased block from the pre-erase block heap.
17. The data storage device of claim 16 , the controller being further configured to erase data in the free block with a single layer cell (SLC) erase.
18. The data storage device of claim 17 , the controller being further configured to maintain the erased block in an erased state.
19. The data storage device of claim 18 , the controller being further configured to store the pre-erase block heap in a flash translation layer means.
20. The data storage device of claim 19 , the controller being further configured to update the pre-erase block heap upon an allocation of the erased block in response to a command from a host.