Data storage with improved cache read
The present disclosure generally relates to optimizing memory storage performance and power usage. Read operations from flash memory are comprised of a sense operation and a read transfer operation. Usually, these two operations are performed in parallel to achieve high read performance. However, these two operations typically do not take the same amount of time, leading to inefficiencies. By measuring sense busy time, the read transfer clock may be set accordingly so the two operations are equal in time. In so doing, the system will be optimized from both a performance and power consumption point of view.
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
collect information about current transfer size of a read operation;
determine an expected busy time, wherein the expected busy time is a time to perform a sense operation;
calculate a transfer clock frequency; and
set the transfer clock frequency, wherein the transfer clock frequency of at least one memory die is different than a transfer clock frequency of at least one other die, wherein calculating the transfer clock frequency is determined individually per the at least one memory die, wherein a total combined transfer time of the at least one memory die is equal to the expected busy time.
2. The data storage device of claim 1 , wherein the collecting information is a dynamic process of collecting current transfer size and expected busy time per current sense.
3. The data storage device of claim 2 , wherein the expected busy time depends upon several parameters including die size, silicon process type, and other parameters defined inside flash memory.
4. The data storage device of claim 1 , wherein the calculating and setting the transfer clock frequency occurs per sense.
5. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
perform a dummy read from the memory device for a predetermined transfer size;
measure a busy time of sensing of the dummy read;
calculate a transfer clock frequency; and
dynamically adjust the transfer clock frequency for future read operations, wherein performing the dummy read comprises performing a dummy operation for expected varieties of future operations, wherein a busy time for each dummy read performed is recorded in a table.
6. The data storage device of claim 1 , wherein the calculating the transfer clock frequency comprises a toggle mode, wherein the transfer clock frequency is set to a maximum possible frequency while the toggle mode is active.
7. The data storage device of claim 1 , wherein collecting information about the current transfer size comprises adding a size of read data and a size of error correction data associated with the read data.
8. The data storage device of claim 1 , wherein determining an expected busy time comprises identifying a random read operation and setting the expected busy time to a minimum value.
9. The data storage device of claim 1 , wherein the controller is further configured to adjust a transfer clock frequency so that a transfer time will be less than the expected busy time.
10. The data storage device of claim 1 , wherein the busy time is calculated according to the following formula: (1/Frequency)*Transfer size(+ECC)=busy time.
11. The data storage device of claim 5 , wherein dynamically adjusting the transfer clock frequency for future read operations comprises calculating a second transfer clock frequency for a second read operation based upon transfer size of the second read operation.
12. The data storage device of claim 5 , wherein calculating the transfer clock frequency comprises determining transfer size and error correction size of a current read operation to calculate the transfer clock frequency to match expected busy time.
13. The data storage device of claim 5 , wherein the data storage device further comprises a plurality of memory devices coupled to the controller.
14. The data storage device of claim 13 , wherein the plurality of memory devices are coupled to one or more transfer clocks.
15. A data storage device, comprising:
memory means; and
a controller coupled to the memory means, wherein the controller is configured to:
receive a read command from a host;
determine data transfer parameters associated with the read command and an expected busy time of sensing the data; and
adjust a transfer clock frequency so that a transfer time will be less than the expected busy time.
16. The data storage device of claim 15 , wherein the data storage device further comprises an Error Correction Code (ECC) module for decoding read data.
17. The data storage device of claim 16 , wherein the data transfer parameters associated with the read command and an expected busy time of sensing the data comprises current transfer size, ECC size, die size, and silicon process type.
18. The data storage device of claim 16 , wherein adjusting the transfer clock frequency so that the transfer time will be less than the expected busy time comprises shortening the transfer time by an amount of time for the ECC module to decode the data.
19. The data storage device of claim 18 , wherein the controller is further configured to determine when a program erase cycle is over a threshold and adjust the transfer clock frequency to be less by a greater amount to allow more time for the ECC module to decode.
20. The data storage device of claim 5 , wherein the dynamically adjusting comprises adjusting a transfer clock frequency so that a transfer time will be less than the expected busy time.