Leaky memory hole repair at fabrication joint
A memory array with a fabrication joint includes a controller configured to apply a detection voltage on a word line coupled to a plurality of bitlines, count a number of bitlines having a first type of response to the detection voltage, and on condition that the number of bitlines exceeds a configured value, program memory cells on at least one dummy word line adjacent to the fabrication joint with a particular threshold voltage.
1. A memory device comprising:
a memory array having memory channels, each memory channel having memory cells and a fabrication joint; and
a controller configured to:
program the memory cells of the memory channels with user data;
detect a number of memory cells that failed to program correctly with the user data in response to the memory cells satisfying a threshold;
determine bitlines corresponding to the memory cells that failed to program correctly;
increase a threshold voltage for particular dummy memory cells on at least one dummy word line adjacent to a fabrication joint of memory channels connected to the determined bitlines, the particular dummy memory cells positioned within the memory channels connected to the determined bitlines; and
wherein the threshold voltage is configured to mitigate current leakage between adjacent memory channels.
2. The memory device of claim 1 , wherein detecting the number of memory cells that failed to program correctly comprises subtracting a first number of bitlines not satisfying the threshold from a total number of bitlines on a word line.
3. The memory device of claim 1 , the controller further configured to:
apply a detection voltage satisfying a highest successful program threshold voltage and determine the number of the memory cells that failed to program correctly in response to a programming failure.
4. The memory device of claim 3 , the controller further configured to:
in response to the programming failure, perform a backup of data in a memory region in which the programming failure occurred;
mark the memory region as unavailable for use;
increase the threshold voltage for the at least one dummy memory cell on the at least one dummy word line adjacent to the fabrication joint; and
mark the memory region as available for use.
5. The memory device of claim 3 , the controller further configured to:
detect the number of the memory cells that failed to program correctly only for a single particular word line of a plurality of word lines of the memory array.
6. The memory device of claim 5 , wherein the single particular word line is word line 0 .
7. The memory device of claim 5 , the controller further configured to:
determine the number of the memory cells that failed to program correctly on condition that the programming failure occurs on the single particular word line.
8. The memory device of claim 1 , the controller further configured to:
initialize a region of the memory array comprising the memory channels with a random data pattern.
9. An apparatus comprising:
a controller configured to:
program memory cells of a memory array comprising a fabrication joint, by setting threshold voltages on the memory cells;
detect a number of memory cells that failed to program correctly in response to applying a detection voltage on at least one word line of the memory array;
determine one or more bitlines corresponding to the memory cells that failed to program correctly; and
program particular dummy memory cells on at least one dummy word line adjacent to the fabrication joint, the particular dummy memory cells programmed to a particular threshold voltage configured to mitigate current leakage between memory channels of the memory cells that failed to program correctly.
10. The apparatus of claim 9 , wherein detecting the number of the memory cells that failed to program correctly comprises subtracting a first number of bitlines not responding to the detection voltage from a total number of bitlines subjected to the detection voltage.
11. The apparatus of claim 9 , the detection voltage satisfying a highest successful program threshold voltage for the memory cells.
12. The apparatus of claim 11 , further configured to:
in response to a programming failure, perform a backup of data in a memory region in which the programming failure occurred;
repair memory channels corresponding to the memory cells that failed to program correctly;
detect the number of memory cells that failed to program in response to applying the detection voltage on at least one word line selected for programming; and
mark the memory region as available for use.
13. The apparatus of claim 11 , further configured to:
detect the number of the memory cells that failed to program correctly only for a single particular word line of a plurality of word lines of the memory array.
14. The apparatus of claim 13 , wherein the single particular word line is word line 0 .
15. The apparatus of claim 13 , further configured to:
determine the number of the memory cells that failed to program correctly on condition that a programming failure occurs on the single particular word line.
16. The apparatus of claim 9 , further configured to:
initialize a region of the memory array comprising the memory cells with a random data pattern.
17. An apparatus comprising:
memory means comprising memory cells and a fabrication joint;
means for detecting a number of memory cells that failed to program correctly in response to applying a detection voltage on at least one word line of the memory means; and
means for increasing a threshold voltage for particular dummy memory cells on at least one dummy word line adjacent to the fabrication joint, the particular dummy memory cells located within memory channels of the memory cells that failed to program correctly and wherein the particular dummy memory cells acquire a particular threshold voltage configured to mitigate current leakage between memory channels of the memory cells that failed to program correctly.
18. The apparatus of claim 17 , further comprising means for performing a backup of data from the memory means.
19. The apparatus of claim 17 , further comprising:
means for detecting the number of the memory cells that failed to program correctly only for a single particular word line of a plurality of word lines of the memory means.
20. The apparatus of claim 19 , wherein the single particular word line is word line 0 .