IP Library Granted Patent US 12,093,130
Granted Patent B2
US 12,093,130 · App. 17/725,367 · Granted Sep 17, 2024

Read look ahead optimization according to NVMe dataset management hints

Inventors: Alexander Bazarsky (Holon, IL); Judah Gamliel Hahn (Ofra, IL); Michael Ionin (Rehovot, IL)
Assignee: Sandisk Technologies, Inc.
G06F11/1068G06F3/0619G06F3/064G06F3/0659G06F3/0679G06F11/0772
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Quick Facts
Patent No.
US 12,093,130
App. No.
17/725,367
Granted
Sep 17, 2024
Kind
B2
Abstract

A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a dataset management (DSM) hint, determine if a second physical memory range associated with a next read operation is located within a threshold number of physical block addresses (PBAs) to a first physical memory range associated with a current read operation, where the next read operation is provided by the DSM hint, and utilize at least a portion of a latency budget associated with the current read operation to optimize a read parameter of the first physical memory range.

Claims (56)

1. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

receive a dataset management (DSM) hint from a host device;

determine if a second physical memory range associated with a next read operation is located within a threshold number of physical block addresses (PBAs) to a first physical memory range associated with a current read operation, wherein the next read operation is provided by the DSM hint;

utilize at least a portion of a latency budget associated with the current read operation to reduce a read latency of a read parameter of the first physical memory range;

determine if a time remaining exceeds or equals a minimum time threshold, wherein the minimum time threshold corresponds to a time to perform a recovery operation segment for the first physical memory range; and

perform the recovery operation segment on the first physical memory range when the time remaining exceeds or equals the minimum time threshold.

2. The data storage device of claim 1 , wherein the utilizing occurs when the second physical memory range is located within the threshold number of PBAs to the first physical memory range.

3. The data storage device of claim 1 , wherein the determining comprises comparing PBAs of the first physical memory range to PBAs of the second physical memory range.

4. The data storage device of claim 3 , wherein the comparing comprises comparing a first time tag of the PBAs of the first physical memory range and a second time tag of the PBAs of the second physical memory range.

5. The data storage device of claim 3 , wherein the comparing comprises comparing a first temperature tag of the PBAs of the first physical memory range and a second temperature tag of the PBAs of the second physical memory range.

6. The data storage device of claim 1 , wherein the controller is further configured to perform read level tracking (RLT) on the first physical memory range after reducing a read latency of the read parameter of the first physical memory range.

7. The data storage device of claim 6 , wherein the controller is further configured to calibrate a read parameter of the second physical memory range based on the reduced read latency read parameter of the first physical memory range.

8. The data storage device of claim 1 , wherein the controller is further configured to:

when the second physical memory range is not located within the threshold number of PBAs to the first physical memory range, determine if a RLA hard bit (HB) decode has failed; and

determine if a third physical memory range associated with a next host read is located within the threshold number of PBAs to the second physical memory range, wherein the determining comprises comparing the PBAs of the second physical memory range to PBAs of the third physical memory range.

9. The data storage device of claim 8 , wherein the controller is further configured to:

determine that the third physical memory range is located within the threshold number of PBAs to the second physical memory range; and

apply read level tracking (RLT) to calibrate a read threshold of the second physical memory range.

10. The data storage device of claim 9 , wherein the calibrated read threshold is applied to the third physical memory range.

11. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

determine that a received dataset management (DSM) hint indicates that a read look ahead (RLA) read for a first physical memory range will be needed;

perform a read recovery flow on a first physical memory range;

determine that a decode operation on the first physical memory range has failed;

determine that a second physical memory range associated with a next host read is located within a threshold number of physical block addresses (PBAs) to the first physical memory range;

determine if a time remaining exceeds or equals a minimum time threshold, wherein the minimum time threshold corresponds to a time to perform a recovery operation segment for the first physical memory range;

perform the recovery operation segment on the first physical memory range when the time remaining exceeds or equals the minimum time threshold;

perform read level tracking (RLT) on the first physical memory range and the second physical memory range; and

adjust a read threshold of the first physical memory range and the second physical memory range.

12. The data storage device of claim 11 , wherein the next host read is provided in a second received DSM hint.

13. The data storage device of claim 11 , wherein the controller is further configured to:

determine that another RLA read decode operation has failed, wherein the another RLA read is on a third physical memory range that is located within the threshold number of PBAs to the first physical memory range or the second physical memory range;

perform a HB read on the third physical memory range using the adjusted read threshold; and

re-decode the third physical memory range.

14. The data storage device of claim 13 , wherein the controller is further configured to:

determine that the re-decoding has failed; and

resume a standard read recovery operation.

15. The data storage device of claim 11 , wherein the controller is further configured to:

determine that the first physical memory range has a higher risk of failing a hard bit (HB) decode relative to the second physical memory range; and

re-order a plurality of next read operations.

16. The data storage device of claim 11 , wherein the recovery operation segment comprises at least a read threshold calibration, a soft bit (SB) read, a decode of the SB read, and exclusive or (XOR) recovery.

17. A data storage device, comprising:

memory means; and

a controller coupled to the memory means, wherein the controller is configured to:

apply a result of a read threshold calibration of a first physical memory range to a second physical memory range, wherein:

a dataset management (DSM) hint provides the controller with the second physical memory range; and

at least a portion of a latency budget associated with the first physical memory range associated with a current read operation is utilized to perform the read threshold calibration;

determine if a time remaining exceeds or equals a minimum time threshold, wherein the minimum time threshold corresponds to a time to perform a recovery operation segment for the first physical memory range;

perform the recovery operation segment on the first physical memory range when the time remaining exceeds or equals the minimum time threshold; and

re-order a plurality of read commands based on the result of the read threshold calibration.

18. The data storage device of claim 17 , wherein the second physical memory range is located within a threshold number of physical block addresses (PBAs) to the first physical memory range.

19. The data storage device of claim 17 , wherein the read threshold calibration is a read level tracking (RLT) operation.

20. The data storage device of claim 17 , wherein the plurality of read commands are re-ordered such that a next read command of the plurality of read commands that are expected to have a low latency impact are completed first.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 21, 2022
From: BAZARSKY, ALEXANDER; HAHN, JUDAH GAMLIEL; IONIN, MICHAEL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059664/0638 →