IP Library Granted Patent US 11,462,497
Granted Patent B2
US 11,462,497 · App. 17/174,657 · Granted Oct 4, 2022

Semiconductor device including coupled bond pads having differing numbers of pad legs

Inventors: Kirubakaran Periyannan (Santa Clara, CA); Daniel Linnen (Naperville, IL); Jayavel Pachamuthu (San Jose, CA)
Assignee: Western Digital Technologies, Inc.
H01L24/08H01L24/05H01L2224/05557H01L2224/0807H01L2224/08145
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Quick Facts
Patent No.
US 11,462,497
App. No.
17/174,657
Granted
Oct 4, 2022
Kind
B2
Abstract

A semiconductor device including an integrated module formed of a first semiconductor die coupled to a second semiconductor die. Each of the first and second semiconductor dies includes a number of bond pads, which are bonded to each other to form the integrated module. Each bond pad may be divided into a number of discrete pad legs. While the overall footprint of each bond pad on the first and second semiconductor dies may be the same, the bond pads on one of the dies may have a larger number of pad legs.

Claims (34)

1. An integrated module comprising:

a first component comprising at least a first group of bond pads, a first bond pad of the first group of bond pads divided into a first plurality of pad legs; and

a second component comprising a second group of bond pads, a second bond pad of the second group of bond pads divided into a second plurality of pad legs, there being a different number of pad legs in the second plurality of pad legs than in the first plurality of pad legs, the second bond pad coupled to the first bond pad to electrically and physically couple the second component to the first component;

wherein the different numbers of pad legs on the first and second bond pads are provided so that one or more of the pad legs of the first plurality of pad legs align with one or more of the pad legs of the second plurality of pad legs in at least one of two orthogonal directions, where the first and second bond pads are aligned with each other or misaligned with each other.

2. The integrated module of claim 1 , wherein the first and second bond pads each have a length in a first direction and a length in a second direction orthogonal to the first direction, and wherein the number of pad legs of the first and second bond pads are different in the first direction and in the second direction.

3. The integrated module of claim 1 , wherein the first and second bond pads each have a length in a first direction and a length in a second direction orthogonal to the first direction, and wherein the number of pad legs of the first and second bond pads are the same in one of the first and second directions.

4. The integrated module of claim 1 , wherein the first and second bond pads each have a length in a first direction and a length in a second direction orthogonal to the first direction, and wherein the number of pad legs in the first plurality of pad legs in the first direction is one less than the number of pad legs in the second plurality of pad legs in the first direction.

5. The integrated module of claim 1 , wherein the first and second bond pads each have a length in a first direction and a length in a second direction orthogonal to the first direction, and wherein the number of pad legs in the first plurality of pad legs in the first direction is between one and ten less than the number of pad legs in the second plurality of pad legs in the first direction.

6. The integrated module of claim 1 , wherein a size of a pad leg in the first plurality of pad legs is different along a first direction than a size of a pad leg in the second plurality of pad legs along the first direction.

7. The integrated module of claim 1 , wherein a pitch between pad legs in the first plurality of pad legs is different along a first direction than a pitch between pad legs in the second plurality of pad legs along the first direction.

8. The integrated module of claim 1 , wherein the first and second components comprise first and second semiconductor dies.

9. The integrated module of claim 8 , wherein the first semiconductor die comprises a plurality of memory cells, and the second semiconductor die comprises a control circuit for controlling access to the plurality of memory cells.

10. An integrated module comprising:

a first semiconductor die comprising at least a first group of bond pads, a first bond pad of the first group of bond pads divided into a first plurality of pad legs; and

a second semiconductor die comprising a second group of bond pads, a second bond pad of the second group of bond pads divided into a second plurality of pad legs;

wherein a first set of one or more pad legs of the first plurality of plurality of pad legs aligns with a second set of one or more pad legs of the second plurality of pad legs when the first and second bond pads are aligned with each other upon being coupled; and

wherein a third set of one or more pad legs of the first plurality of plurality of pad legs aligns with a fourth set of one or more pad legs of the second plurality of pad legs when the first and second bond pads are misaligned with each other upon being coupled.

11. The integrated module of claim 10 , wherein there is a different number of pad legs in the first plurality of pad legs than there are in the second plurality of pad legs.

12. The integrated module of claim 10 , wherein a size of the pad legs in the first plurality of pad legs is different than a size of the pad legs in the second plurality of pad legs.

13. The integrated module of claim 12 , wherein the size of the pad legs in the first plurality of pad legs is different in only one dimension than the size of the pad legs in the second plurality of pad legs.

14. The integrated module of claim 12 , wherein the size of the pad legs in the first plurality of pad legs is different in first and second orthogonal dimensions than the size of the pad legs in the second plurality of pad legs.

15. The integrated module of claim 10 , wherein a pitch between the pad legs in the first plurality of pad legs is different than a pitch between the pad legs in the second plurality of pad legs.

16. The integrated module of claim 15 , wherein the pitch between the pad legs in the first plurality of pad legs is different in only one dimension than the pitch between the pad legs in the second plurality of pad legs.

17. The integrated module of claim 15 , wherein the pitch between the pad legs in the first plurality of pad legs is different in first and second orthogonal dimensions than the pitch between the pad legs in the second plurality of pad legs.

18. The integrated module of claim 10 , wherein the integrated module comprises an integrated memory module.

19. An integrated module comprising:

a first semiconductor die comprising at least a first group of bond pads, a first bond pad of the first group of bond pads divided into a first plurality of pad legs; and

a second semiconductor die comprising a second group of bond pads, a second bond pad of the second group of bond pads divided into a second plurality of pad legs;

means for aligning a first set of one or more pad legs of the first plurality of plurality of pad legs with a second set of one or more pad legs of the second plurality of pad legs when the first and second bond pads are aligned with each other upon being coupled; and

means for aligning a third set of one or more pad legs of the first plurality of plurality of pad legs with a fourth set of one or more pad legs of the second plurality of pad legs when the first and second bond pads are misaligned with each other upon being coupled.

20. An integrated module comprising:

a first component comprising at least a first group of bond pads, a first bond pad of the first group of bond pads divided into a first plurality of pad legs; and

a second component comprising a second group of bond pads, a second bond pad of the second group of bond pads divided into a second plurality of pad legs, there being a different number of pad legs in the second plurality of pad legs than in the first plurality of pad legs, the second bond pad coupled to the first bond pad to electrically and physically couple the second component to the first component;

wherein the first and second bond pads each have a length in a first direction and a length in a second direction orthogonal to the first direction, and wherein the number of pad legs of the first and second bond pads are the same in one of the first and second directions.

Assignments (10)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 12, 2021
From: PERIYANNAN, KIRUBAKARAN; LINNEN, DANIEL; PACHAMUTHU, JAYAVEL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055243/0835 →