IP Library Granted Patent US 11,200,003
Granted Patent B2
US 11,200,003 · App. 16/925,185 · Granted Dec 14, 2021

Bounded latency and command non service methods and apparatus

Inventors: Neil Hutchison (Hudsonville, MI); Peter Grayson (Grand Rapids, MI); Xinde Hu (San Jose, CA); Daniel L. Helmick (Broomfield, CO); Rodney Brittner (San Jose, CA)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F3/0659G06F3/0611G06F3/0673G06F11/0757G06F12/0246G06F13/161G06F13/1642G06F2201/81G06F2201/835G06F2212/1024
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Quick Facts
Patent No.
US 11,200,003
App. No.
16/925,185
Granted
Dec 14, 2021
Kind
B2
Abstract

The present disclosure generally presents a method and apparatus to provide a bounded latency, where a device would report “non-service” of a command at the defined system level timeout or earlier if the device was unable to successfully return the data to the host.

Claims (63)

1. A solid state drive, comprising:

a controller configured to:

receive one or more commands at a flash translation layer;

timestamp each command received at the flash translation layer, a timestamp of the respective command indicating a time when a latency threshold of the respective command will be exceeded;

add each command received at the flash translation layer to a queue;

determine, for a next command to be performed in the queue, whether the respective command has timed out before being transferred from the queue for being performed based on the timestamp of the respective command; and

send, for a command that has been determined to be timed out, a message to a host that the respective command has timed out.

2. The solid state drive of claim 1 , wherein receiving the one or more commands at the flash translation layer includes receiving multiple commands at the flash translation layer.

3. The solid state drive of claim 1 , wherein the flash translation layer is disposed in a memory device, and the memory device performs the receiving the one or more commands, the timestamping each command, the adding the command to the queue, the determining whether a command has timed out, and the sending the message to the host.

4. The solid state drive of claim 1 , wherein the controller is further configured to:

remove from the queue each command that has been determined to be timed out.

5. The solid state drive of claim 1 , further comprising:

an interface, wherein the interface is configured to:

timestamp each command received at the flash translation layer, a timestamp of the respective command indicating a time when a latency threshold of the respective command will be exceeded;

manage one or more data requests from flash memory;

determine instances of when a timed out condition is present; and

limit the flash translation layer from sending timed out conditions for activities that have already been notified as timed out.

6. The solid state drive of claim 1 , further comprising:

one or more flash memories coupled to the controller, wherein the one or more flash memories store data associated with the one or more commands.

7. The solid state drive of claim 6 , wherein the one or more flash memories comprises one or more dies.

8. A solid state drive, comprising:

a controller is configured to:

receive one or more commands at a flash translation layer, wherein each command is required to be performed at a specified die;

timestamp each command received at the flash translation layer, a timestamp of the respective command indicating a time when a latency threshold of the respective command will be exceeded;

add each command received at the flash translation layer to a queue;

determine, for a next command to be performed in the queue, whether the respective command has timed out before being transferred to the specified die based on the timestamp of the respective command;

send, for a command that has been determined to be timed out, a message to a host that the respective command has timed out;

determine, for a next command to be performed in the queue that has not timed out, whether the respective command is expected to time out based on a latency for completion and the timestamp of the respective command, the latency for completion being based on a number of commands to be processed (i) before the respective command and (ii) by the specified die that is to perform the respective command; and

notify, for a next command that is determined to be expected to time out, the host that the respective command is expected to time out.

9. The solid state drive of claim 8 , wherein receiving the one or more commands at the flash translation layer includes receiving multiple commands at the flash translation layer.

10. The solid state drive of claim 8 , wherein the controller is further configured to:

remove from the queue each command that has been determined to be timed out.

11. The solid state drive of claim 8 , wherein the controller is further configured to:

determine, for each command in the queue, whether the respective command has timed out before being transferred to the specified die based on the timestamp of the respective command; and

determine, for each command in the queue that has not timed out, whether the respective command is expected to time out based on the respective latency for completion and the timestamp of the respective command.

12. The solid state drive of claim 8 , further comprising:

an interface, wherein the interface is configured to:

timestamp each command received at the flash translation layer, a timestamp of the respective command indicating a time when a latency threshold of the respective command will be exceeded;

manage one or more data requests from flash memory;

determine instances of when a timed out condition is present; and

limit the flash translation layer from sending timed out conditions for activities that have already been notified as timed out.

13. The solid state drive of claim 8 , further comprising:

one or more flash memories coupled to the controller, wherein the one or more flash memories store data associated with the one or more commands.

14. The solid state drive of claim 13 , wherein the one or more flash memories comprises one or more dies.

15. A solid state drive, comprising:

a controller is configured to:

receive one or more commands at a flash translation layer, wherein each command is required to be performed at a specified die;

timestamp each command received at the flash translation layer, a timestamp of the respective command indicating a time when a latency threshold of the respective command will be exceeded;

add each command received at the flash translation layer to a queue;

determine, for a next command to be performed in the queue that has not timed out, whether the respective command is expected to time out based on a latency for completion and the timestamp of the respective command, the latency for completion being based on a number of commands to be processed (i) before the respective command and (ii) by the specified die that is to perform the respective command; and

notify, for a next command that is determined to be expected to time out, a host that the respective command is expected to time out.

16. The solid state drive of claim 15 , wherein receiving the one or more commands at the flash translation layer includes receiving multiple commands at the flash translation layer, wherein the multiple commands are to be performed by a memory arrangement.

17. The solid state drive of claim 15 , wherein the controller is further configured to:

remove from the queue each command that has been determined to be timed out.

18. The solid state drive of claim 15 , further comprising:

an interface, wherein the interface is configured to:

timestamp each command received at the flash translation layer, a timestamp of the respective command indicating a time when a latency threshold of the respective command will be exceeded;

manage one or more data requests from flash memory;

determine instances of when a timed out condition is present; and

limit the flash translation layer from sending timed out conditions for activities that have already been notified as timed out.

19. The solid state drive of claim 15 , further comprising:

one or more flash memories coupled to the controller, wherein the one or more flash memories store data associated with the one or more commands.

20. The solid state drive of claim 19 , wherein the one or more flash memories comprises one or more dies.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 13, 2020
From: HUTCHISON, NEIL; GRAYSON, PETER; HU, XINDE; HELMICK, DANIEL; BRITTNER, RODNEY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 053191/0868 →
Cited By (1)
US 12,664,090