IP Library Granted Patent US 11,847,343
Granted Patent B2
US 11,847,343 · App. 17/559,327 · Granted Dec 19, 2023

Storage system and method for non-blocking coherent re-writes

Inventors: Eyal Sobol (Givat Shmuel, IL); Karin Inbar (Kfar Saba, IL); Avi Shchislowski (Kadima, IL); Yuliy Izrailov (Rishon LeZion, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0655G06F3/0604G06F3/0679
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Quick Facts
Patent No.
US 11,847,343
App. No.
17/559,327
Granted
Dec 19, 2023
Kind
B2
Abstract

A host sends a storage system a command to read data from a memory and then a command to write the data back to the memory to defragment the data. The host sends flags along with the commands. The flag sent with the read command causes the storage system to take a snapshot of the logical-to-physical address map relevant to the data. The flag sent with the write command causes the storage system to compare the snapshot with the current version of the logical-to-physical address map and write the data back to the memory only if there is a match.

Claims (32)

1. A storage system comprising:

a memory; and

a controller coupled to the memory and configured to:

in response to receiving a read command from a host to read data stored at a logical block address of the memory:

read the data from the memory; and

store a representation of a portion of a logical-to-physical address table that contains an entry for the logical block address; and

in response to receiving a write command from the host to write the data back to the memory:

compare the representation with a current version of the portion of the logical-to-physical address table that contains the entry for the logical block address; and

write the data back to the memory only in response to the representation matching the current version.

2. The storage system of claim 1 , wherein the controller is further configured to receive information from the host that causes the controller to store the representation in the memory and compare the representation with the current version.

3. The storage system of claim 1 , wherein the read command comprises a first flag configured to cause the controller to store the representation in the memory, and wherein the write command comprises a second flag configured to cause the controller to compare the representation with the current version.

4. The storage system of claim 3 , wherein the first flag is stored in a reserved parameter in the read command.

5. The storage system of claim 3 , wherein the second flag is stored in a reserved parameter in the write command.

6. The storage system of claim 3 , wherein the first flag comprises a non-blocking coherent re-write process read flag, and wherein the second flag comprises a non-blocking coherent re-write process write flag.

7. The storage system of claim 1 , wherein the data is read by the controller from non-sequential physical addresses in the memory and is written back by the controller to sequential physical addresses in the memory.

8. The storage system of claim 1 , wherein the controller is further configured to update the logical-to-physical address table after writing the data back to the memory.

9. The storages system of claim 1 , wherein the controller is further configured to store the representation in the memory and compare the representation with the current version in response to a fragmentation level of the data being above a threshold.

10. The storages system of claim 1 , wherein the controller is further configured to not write the data back to the memory in response to the representation not matching the current version.

11. The storage system of claim 1 , wherein the read and write commands are of a fixed size.

12. The storage system of claim 1 , wherein joint synchronized processes on the host and the controller are configured to cause the data to be written back to the memory only in response to the representation matching the current version.

13. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

14. In a host in communication with a storage system comprising a memory, a method comprising:

sending a read command to the storage system to read data at a logical block address of the memory, wherein the read command comprises a first flag configured to cause the storage system to take a snapshot of a segment of a logical-to-physical address table that is relevant to the logical block address; and

sending a write command to the storage system to write the data back to the memory, wherein the write command comprises a second flag configured to cause the storage system to compare the snapshot with a current version of the segment of the logical-to-physical address table and write the data back to the memory only in response to the snapshot matching the current version.

15. The method of claim 14 , wherein the first flag is stored in a reserved parameter in the read command.

16. The method of claim 14 , wherein the second flag is stored in a reserved parameter in the write command.

17. The method of claim 14 , wherein the first flag comprises a non-blocking coherent re-write process read flag, and wherein the second flag comprises a non-blocking coherent re-write process write flag.

18. The method of claim 14 , wherein the read and write commands are of a fixed size.

19. The method of claim 14 , wherein joint synchronized processes on the host and the storage system cause the data to be written back to the memory only in response to the snapshot matching with the current version.

20. A storage system comprising:

a memory; and

means for executing a received write command to write data back to the memory after the data was previously read from the memory, wherein the data is written back to the memory only in response to a portion of a logical-to-physical address table that contains an entry for a logical block address for the data being unchanged from when the data was read from the memory.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2021
From: SOBOL, EYAL; INBAR, KARIN; SHCHISLOWSKI, AVI; IZRAILOV, YULIY
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058461/0964 →
Continuity (1)
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