IP Library Granted Patent US 10,565,115
Granted Patent B2
US 10,565,115 · App. 15/474,340 · Granted Feb 18, 2020

Calculating the optimal number of LBNS to prefetch per CPU

Inventor: Kevin James Wendzel (Rochester, MN)
Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
G06F12/0862G06F2212/602G06F2212/6026G06F2212/7201
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Quick Facts
Patent No.
US 10,565,115
App. No.
15/474,340
Granted
Feb 18, 2020
Kind
B2
Abstract

The present disclosure generally relates to prefetching data from one or more CPUs prior to the data being requested by a host device. The prefetched data is prefetched from memory and stored in cache. If a host device requests data that is not already in cache, then a determination is made regarding whether the data is scheduled to be written into cache. If the data is not in cache and is not scheduled to be written into cache, then the data is retrieved from memory and delivered to the host device. If the data is scheduled to be written into cache, or is currently being written into cache, then the request to retrieve the data is delayed or scheduled to retrieve the data once the data is in cache. If the data is already in cache, the data is delivered to the host device.

Claims (23)

1. A method, comprising:

receiving a first request from a host device to read a first data and a second request to read a second data from a memory device that is coupled to a plurality of CPUs, wherein a first CPU of the plurality of CPUs has a first cache storage and a second CPU of the plurality of CPUs has a second cache storage;

reading the first data from the memory device using the first CPU;

reading the second data from the memory device using the second CPU of the plurality of CPUs;

writing the first data and the second data to the first cache storage of the first CPU;

reading the first and second data from the first cache storage; and

delivering the first and second data to the host device.

2. The method of claim 1 , wherein the memory device is a NAND storage device.

3. The method of claim 1 , wherein the memory device is a hard disk drive storage device.

4. A method, comprising:

receiving a first request from a host device to read a first LBA data from a a first LBN and a second LBN disposed in a memory device that is coupled to a first CPU and a second CPU, wherein the first CPU has a first cache storage and is assigned the first LBN, wherein the second CPU has a second cache storage and is assigned the second LBN;

reading a first portion of the first LBA data from the first LBN of the memory device;

reading a second portion of the first LBA data from the second LBN of the memory device;

writing the first portion of the first LBN data and the second portion of the first LBN data to the first cache storage;

reading the first LBA data from the first cache storage; and

delivering the first LBA data to the host device.

5. The method of claim 4 , further comprising:

receiving a second request from the host device to read a second LBA data from the memory device, wherein the first LBA data and the second LBA data are sequential data;

reading the second LBA data from the memory device;

writing the second LBA data to the first cache storage; and

delivering the second LBA data to the host device.

6. The method of claim 5 , wherein the writing the second LBA data to the first cache storage occurs prior to receiving the second request.

7. The method of claim 4 , wherein the reading the first portion of the first LBA data is performed by the first CPU and reading the second portion of the first LBA data is performed by the second CPU.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 30, 2017
From: WENDZEL, KEVIN JAMES
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 041799/0934 →
Continuity (1)
Related Publication 20180285273A1 · Oct 4, 2018