Granted Patent B2

US 11,798,627 · App. 17/356,408 · Granted Oct 24, 2023

Inventors: Sergey Anatolievich Gorobets (Edinburgh, GB); Xinmiao Zhang (Mercer Island, WA); James Fitzpatrick (Laguna Niguel, CA)

Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.

G11C16/10G06F11/1068G06F11/1072G11C16/26

Abstract

Claims (58)

1. A method implemented for one or more storage devices, the method comprising:

writing, in a first phase, a first portion of data into memory cells of a memory in a first-level cell mode;

regenerating the data, wherein the regenerated data comprises a second portion of the data; and

writing, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode,

wherein:

the first-level cell mode is for storing a first number of bits per cell, and the second-level cell mode is for storing a second number of bits per cell;

the second number is greater than the first number, and the first number is greater than one;

the mapping maps each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode;

the mapping is configured to provide a width of each state distribution in the first-level cell mode that is less than a combined width of corresponding state distributions in the second-level cell mode; and

the mapping is configured to provide a balanced Gray code in the first-level cell mode and the second-level cell mode,

wherein a difference between transition counts of every two adjacent pages of memory pages in the second-level cell mode does not exceed a predetermined transition count difference, and a sum of the transition counts for all memory pages in the second-level cell mode does not exceed a maximum number of writing levels in the second-level cell mode.

2. The method of claim 1 , comprising:

maintaining, in a storage medium, at least a subset of the data,

wherein regenerating the data comprises regenerating the data from at least the storage medium.

3. The method of claim 1 , wherein the mapping is configured so that the width of each state distribution in the first-level cell mode is approximately half of the combined width of the corresponding state distributions in the second-level cell mode.

4. The method of claim 1 , wherein writing in the first phase and writing in the second phase are executed in a staggered progression across wordlines of the memory cells.

5. The method of claim 2 , wherein regenerating the data from at least the storage medium comprises reading the first portion of the data from the written memory cells and combining the first portion of the data with the subset of the data from the storage medium.

6. The method of claim 2 , wherein the subset of the data comprises the second portion of the data.

7. The method of claim 6 , wherein the subset of the data comprises the first portion of the data.

8. A data storage system, comprising:

memory comprising memory cells; and

one or more controllers configured to cause:

writing, in a first phase, a first portion of data into the memory cells in a first-level cell mode;

regenerating the data, wherein the regenerated data comprises a second portion of the data; and

writing, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode,

wherein:

the first-level cell mode is for storing a first number of bits per cell, and the second-level cell mode is for storing a second number of bits per cell;

the second number is greater than the first number, and the first number is greater than one;

the mapping is configured to map each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode;

the mapping is configured to provide a width of each state distribution in the first-level cell mode that is less than a combined width of corresponding state distributions in the second-level cell mode; and

the mapping is configured to provide a balanced Gray code in the first-level cell mode and the second-level cell mode,

wherein a difference between transition counts of every two adjacent pages of memory pages in the second-level cell mode does not exceed a predetermined transition count difference, and a sum of the transition counts for all memory pages in the second-level cell mode does not exceed a maximum number of writing levels in the second-level cell mode.

9. The data storage system of claim 8 , wherein the one or more controllers are configured to cause:

maintaining, in a storage medium, at least a subset of the data,

wherein regenerating the data comprises regenerating the data from at least the storage medium.

10. The data storage system of claim 8 , wherein the mapping is configured so that the width of each state distribution in the first-level cell mode is approximately half of the combined width of the corresponding state distributions in the second-level cell mode.

11. The data storage system of claim 8 , wherein the one or more controllers are configured to cause: writing in the first phase and writing in the second phase in a staggered progression across wordlines of the memory cells.

12. The data storage system of claim 9 , wherein regenerating the data from at least the storage medium comprises reading the first portion of the data from the written memory cells and combining the first portion of the data with the subset of the data from the storage medium.

13. The data storage system of claim 9 , wherein the subset of the data comprises the second portion of the data.

14. The data storage system of claim 9 , wherein the storage medium is separate and distinct from the memory comprising the memory cells.

15. The data storage system of claim 8 , wherein the one or more controllers are configured to cause maintaining, in a storage medium, no more than the first portion of the data in single-level memory cells.

16. The data storage system of claim 8 , wherein the one or more controllers are configured to cause:

maintaining, in a storage medium, the first portion of the data,

wherein regenerating the data comprises regenerating the data from at least the storage medium based on the first portion of the data.

17. An apparatus, comprising:

means for programming, in a first phase, a first portion of data into memory cells of a memory in a first-level cell mode;

means for regenerating the data, wherein the regenerated data comprises a second portion of the data; and

means for programming, in a second phase, the regenerated data in a second-level cell mode based on a mapping from the first-level cell mode to the second-level cell mode,

wherein:

the first-level cell mode is for storing a first number of bits per cell, and the second-level cell mode is for storing a second number of bits per cell;

the second number is greater than the first number, and the first number is greater than one;

the mapping is configured to map each state distribution in the first-level cell mode to at least two non-adjacent state distributions in the second-level cell mode;

the mapping is configured to provide a width of each state distribution in the first-level cell mode that is less than a combined width of corresponding state distributions in the second-level cell mode; and

the mapping is configured to provide a balanced Gray code in the first-level cell mode and the second-level cell mode,

wherein a difference between transition counts of every two adjacent pages of memory pages in the second-level cell mode does not exceed a predetermined transition count difference, and a sum of the transition counts for all memory pages in the second-level cell mode does not exceed a maximum number of writing levels in the second-level cell mode.

18. The apparatus of claim 17 , comprising:

means for retaining, in a storage medium, at least a subset of the data,

wherein the means for regenerating the data comprises means for regenerating the data from at least the storage medium.

Assignments (10)