Granted Patent B1

US 11,016,905 · App. 16/683,095 · Granted May 25, 2021

Abstract

Claims (58)

1. A method for interfacing with a device including a Storage Class Memory (SCM), the method comprising:

creating a page table including a plurality of entries corresponding to memory locations in the SCM of the device;

setting the plurality of entries as read-only in the page table;

receiving a write request to write byte-addressable data corresponding to a first entry of the plurality of entries;

writing the byte-addressable data for the write request in a buffer of a memory of a host;

receiving a read request to read byte-addressable data corresponding to a second entry of the plurality of entries;

sending a read command to the device to read the byte-addressable data for the read request using a memory device interface; and

redirecting the write request from the memory device interface to a block device interface for performance of the write request.

2. The method of claim 1 , further comprising changing the first entry to indicate read and write access and to point to a location in the memory of the host where the byte-addressable data for the write request was written.

3. The method of claim 1 , further comprising:

reading a block of data for the first entry from the SCM;

storing the read block of data in the buffer of the memory;

modifying the block of data in the buffer to perform the write request; and

sending a write command to the device using a block device interface to flush the modified block of data from the buffer of the memory of the host to the SCM.

4. The method of claim 3 , further comprising:

indicating that data for the first entry in the page table is unavailable for writing data in preparation for the flushing of the modified block of data to the SCM;

setting the first entry as read-only in the page table in response to the completion of the flushing of the modified block of data to the SCM; and

updating the first entry in the page table to point to a location in the SCM where the modified block of data was flushed.

5. The method of claim 1 , wherein the memory device interface accesses a Base Address Register (BAR) of the SCM to read data from the SCM.

6. The method of claim 1 , wherein the write request is performed in the buffer of the memory using an Operating System (OS) and the read command is sent to the device using the memory device interface without using the OS.

7. The method of claim 1 , further comprising communicating with the device using Peripheral Component Interconnect express (PCIe) via the memory device interface and a block device interface.

8. A device, comprising:

a Storage Class Memory (SCM) for storing data; and

control circuitry configured to:

use a block device interface for receiving write commands from a host and writing data in blocks to the SCM and for receiving read commands from the host and reading data in blocks from the SCM; and

use a memory device interface for receiving read commands from the host and reading byte-addressable data from the SCM; and

wherein the block device interface and the memory device interface access the same SCM.

9. The device of claim 8 , wherein the control circuitry is further configured to expose a Base Address Register (BAR) of the device to the host via the memory device interface.

10. The device of claim 8 , wherein the control circuitry is further configured to:

receive a write command from the host via the block device interface to write a block of data in the SCM; and

update addresses used by the memory device interface for byte-addressable data included in the block of data written in the SCM.

11. The device of claim 8 , wherein the control circuitry is further configured to block performance of a write command received via the memory device interface.

12. The device of claim 8 , wherein the control circuitry is further configured to communicate with the host using Peripheral Component Interconnect express (PCIe) via the memory device interface and the block device interface.

13. A host, comprising:

a memory for storing data; and

processor circuitry configured to:

receive a write request to write data corresponding to a first entry of a plurality of entries in a page table;

write data for the write request in a buffer of the memory using an Operating System (OS) of the host;

receive a read request to read data corresponding to a second entry of the plurality of entries in the page table; and

send a read command to a device using a memory device interface without using the OS to read the data for the read request from a Storage Class Memory (SCM) of the device.

14. The host of claim 13 , wherein the processor circuitry is further configured to change the first entry in the page table to indicate read and write access and to point to a location in the memory where data for the write request was written.

15. The host of claim 13 , wherein the processor circuitry is further configured to:

read a block of data for the first entry from the SCM;

store the read block of data in the buffer of the memory;

modify the block of data in the buffer to perform the write request; and

send a write command to the device using a block device interface to flush the modified block of data from the buffer of the memory to the SCM.

16. The host of claim 13 , wherein the processor circuitry is further configured to:

indicate that the first entry in the page table is unavailable for writing data in response to preparing to flush the modified block of data to the SCM;

set the first entry as read-only in the page table in response to the completion of the flushing of the modified block of data to the SCM; and

update the first entry in the page table to point to a location in the SCM where the modified block of data was flushed.

17. The host of claim 13 , wherein the processor circuitry is further configured to redirect the write request from the memory device interface to a block device interface for performance of the write request.

18. The host of claim 13 , wherein the memory device interface accesses a Base Address Register (BAR) of the SCM to read data from the SCM.

19. A device, comprising:

a Storage Class Memory (SCM) for storing data; and

control circuitry configured to:

use a block device interface for receiving write commands from a host to write data in blocks to the SCM and for receiving read commands from the host to read data in blocks from the SCM;

use a memory device interface for receiving read commands from the host to read byte-addressable data from the SCM; and

block performance of a write command received via the memory device interface.

Assignments (10)