Soft bit reference level calibration
Calibration of soft bit reference levels in a non-volatile memory system is disclosed. A set of memory cells are sensed at a hard bit reference level and test soft bit reference levels. The test soft bit reference levels are grouped around the hard bit reference level. A metric is determined for the test soft bit reference levels. Bins are defined based on the hard bit reference level and the set of test soft bit reference levels. A metric may be determined for each of the bins. The new soft bit reference levels are determined based on the metric. In one aspect, the metric is how many memory cells have a value for a physical parameter within each bin. The soft bit reference levels may be established based on a target percentage for the bins. In one aspect, the metric is how many unsatisfied counters are within each bin.
1. An apparatus, comprising:
a communication interface; and
a control circuit coupled to the communication interface, wherein the control circuit is configured to connect to non-volatile memory cells, wherein the control circuit is configured to:
sense a set of non-volatile memory cells at a hard bit reference level and a plurality of lower test soft bit reference levels on a lower side of the hard bit reference level, and a plurality of upper test soft bit reference levels on an upper side of the hard bit reference level, wherein sensing at the hard bit reference level distinguishes between two data states, wherein sensing at the soft bit reference levels indicates reliability of sensing at the hard bit reference level;
determine a metric for each bin in each of a plurality of test groups, wherein each test group comprises bins based on sensing at the hard bit reference level, m of the lower test soft bit reference levels, and m of the upper test soft bit reference levels, wherein a different combination of m of the lower test soft bit reference levels and m of the upper test soft bit reference levels are used for each respective test group, wherein m is a positive integer; and
establish m new lower soft bit reference levels and m new upper soft bit reference levels for sensing the set based on the metrics.
2. The apparatus of claim 1 , wherein:
the metric for each respective bin comprises a percentage of the set having a value for a physical parameter within the respective bin; and
the control circuit is configured to establish the m new lower and m new upper soft bit reference levels based on a target percentage for each respective bin.
3. The apparatus of claim 2 , wherein the control circuit is further configured to:
estimate a bit error rate of data stored in the set; and
establish the target percentage for each respective bin based on the estimated bit error rate of the set.
4. The apparatus of claim 2 , wherein the control circuit is further configured to:
determine a syndrome weight of data stored in the set; and
establish the target percentage based on the syndrome weight.
5. The apparatus of claim 1 , wherein the control circuit is further configured to:
estimate a bit error rate of data read from the set of non-volatile memory cells for different bins for the plurality of test groups; and
establish the m new lower and m new upper soft bit reference levels based on the bit error rates for the different bins.
6. The apparatus of claim 1 , wherein:
the metric comprises unsatisfied counters of data read from the set for different bins for the plurality of test groups; and
the control circuit is further configured to establish the m new lower and m new upper soft bit reference levels based on the unsatisfied counters.
7. The apparatus of claim 6 , wherein the control circuit is further configured to:
determine mutual information based on the unsatisfied counters, wherein the mutual information is between data stored in the set and data read from the set; and
establish the new soft bit reference levels based on the mutual information.
8. The apparatus of claim 7 , wherein the control circuit is further configured to:
establish the new soft bit reference levels to maximize the mutual information.
9. The apparatus of claim 1 , wherein the control circuit is further configured to:
perform N soft bit reads to generate N soft bits for each memory cell in the set;
emulate soft bit reads based on the N soft bits to generate N{circumflex over ( )}2 soft bits for each memory cell in the set; and
determine the metric for each bin based on the N{circumflex over ( )}2 soft bits.
10. A method comprising:
sensing a set of non-volatile memory cells at a hard bit reference level, a plurality of lower test soft bit reference levels on a lower side of the hard bit reference level, and a plurality of upper test soft bit reference levels on an upper side of the hard bit reference level, wherein sensing at the hard bit reference level distinguishes between two data states, wherein sensing at the soft bit reference levels indicates reliability of sensing at the hard bit reference level;
forming a plurality of test cases based on the sensing, wherein each test case includes 2 m+2 bins based on sensing at the hard bit reference level, m of the lower test soft bit reference levels, and m of the upper test soft bit reference levels, wherein a different combination of m of the lower test soft bit reference levels and m of the upper test soft bit reference levels are used for each test case, wherein m is a positive integer;
determining a metric for each bin for each test case; and
establishing m new lower soft bit reference levels and m new upper soft bit reference levels for sensing the set based on the metrics for the plurality of test cases.
11. The method of claim 10 , wherein:
the metric for each bin comprises a count of the memory cells in the set having a value for a physical parameter within the bin; and
establishing the new soft bit reference levels for sensing the set comprises establishing the new soft bit reference levels to correspond to a test case that is selected based on a target count for each of the 2 m+2 bins.
12. The method of claim 11 , further comprising:
estimating a bit error rate of data stored in the set of the memory cells; and
establishing the target count of the memory cells in the set to have a value for a physical parameter within each of the 2 m+2 bins based on the estimated bit error rate.
13. The method of claim 11 , further comprising:
determining a syndrome weight of data read from the set; and
establishing the target count of the memory cells in the set to have a value for a physical parameter within each of the 2 m+2 bins based on the syndrome weight.
14. The method of claim 10 , further comprising:
estimating a bit error rate of data read from the set for different bins using the hard bit reference level and the test soft bit reference levels; and
establishing the new soft bit reference levels based on the bit error rates for different bins.
15. The method of claim 10 , wherein:
determining the metric for the each bin for each test case comprises determining unsatisfied counters of data read from the set using the hard bit reference level and the test soft bit reference levels; and
establishing the new soft bit reference levels is based on the unsatisfied counters.
16. The method of claim 15 , further comprising:
determining mutual information based on the unsatisfied counters, wherein the mutual information is between data stored in the set of memory cells and data read from the set of memory cells; and
establishing the soft bit reference levels that maximizes the mutual information.
17. A non-volatile storage system, comprising:
non-volatile memory cells;
sensing means for sensing a set of the non-volatile memory cells at a hard bit reference voltage, a plurality of lower test soft bit reference voltages having a voltage less than the hard bit reference voltage, and a plurality of upper test soft bit reference voltages having a voltage greater than the hard bit reference voltage, wherein sensing at the hard bit reference voltage distinguishes between two data states, wherein sensing at the soft bit reference voltages indicates reliability of sensing at the hard bit reference voltage; and
control means for establishing m new lower soft bit reference voltages and m new upper soft bit reference voltages for sensing the set based on counts of memory cells in the set having a value for a physical parameter in respective bins in each of a plurality of test groups, wherein each test group includes 2 m+2 bins based on sensing at the hard bit reference voltage, m of the lower test soft bit reference voltages, and m of the upper test soft bit reference voltages, wherein a different combination of m of the lower test soft bit reference voltages and m of the upper test soft bit reference voltages are used for each test case, wherein m is a positive integer.
18. The non-volatile storage system of claim 17 , wherein the control means is further for:
accessing a target bin count for each of the 2 m+2 bins; and
establishing the new soft bit reference voltages based on a test group having bins with counts closest to the target bin counts.
19. The non-volatile storage system of claim 18 , wherein the control means is further for:
estimating a bit error rate of data read from the set of memory cells using the hard bit reference voltage and current values of the soft bit reference voltages; and
selecting the target bin count based on the estimated bit error rate.
20. The non-volatile storage system of claim 18 , wherein the control means is further for:
determining a syndrome weight of data read from the set of memory cells using the hard bit reference voltage and present values of the soft bit reference voltages; and
selecting the target bin counts based on the syndrome weight.