IP Library Granted Patent US 12,327,031
Granted Patent B2
US 12,327,031 · App. 17/900,276 · Granted Jun 10, 2025

Compaction of a logical-to-physical table for zoned namespace nonvolatile memory

Inventors: Avinash Muthya Narahari (Bangalore, IN); Rajthilak Dasarathan (Tiruchirappalli, IN)
Assignee: Sandisk Technologies, Inc.
G06F3/064G06F3/0604G06F3/0652G06F3/0679
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Quick Facts
Patent No.
US 12,327,031
App. No.
17/900,276
Granted
Jun 10, 2025
Kind
B2
Abstract

A Zoned Namespace data storage device configured to perform logical-to-physical (L2P) address translation using first and second L2P tables of different respective granularities. In an example embodiment, the first L2P table has a finer (e.g., page-level) granularity and is used to perform L2P address translation for open zones. The second L2P table has a coarser (e.g., erase-block) granularity and is used to perform L2P address translation for finished zones. A controller of the data storage device performs granularity-changing transfers of L2P entries between the first and second L2P tables in response to a respective open zone becoming finished and in response to a new zone becoming open. The coarser granularity of the second L2P table enables the full L2P table to have a relatively small size, which can beneficially be used to make more space available in the same amount of RAM for other operations.

Claims (85)

1. A data storage device, comprising:

a nonvolatile memory having a plurality of superblocks thereof mapped to a plurality of zones, each of the plurality of zones being of a type requiring sequential write of host data, an erase block being a minimum erasable unit of the plurality of superblocks; and

a controller coupled to the nonvolatile memory and configured to perform logical-to-physical (L2P) address translation using a first L2P table and a second L2P table;

wherein the first L2P table includes one or more first L2P sub-tables, each of the one or more first L2P sub-tables having a first granularity and assigned to a respective open zone of the plurality of zones;

wherein the second L2P table includes one or more second L2P sub-tables, each of the one or more second L2P sub-tables having an erase-block granularity and assigned to a respective full zone of the plurality of zones, the first granularity being finer than the erase-block granularity;

wherein the controller is configured to perform a compacting sub-table transfer from the first L2P table to the second L2P table in response to detecting a finishing of the respective open zone; and

wherein the controller is configured to perform the L2P address translation of a host logical address by obtaining a corresponding sub-address combination including:

a physical address of a corresponding erase block;

a corresponding word-line number;

a corresponding string-line number;

a corresponding page-type identifier; and

a corresponding page offset.

2. The data storage device of claim 1 ,

wherein a page is a minimum writable unit of the plurality of superblocks; and

wherein the first granularity is a page-level granularity.

3. The data storage device of claim 1 ,

wherein each of the plurality of superblocks includes a first fixed number of erase blocks;

wherein each of the first fixed number of the erase blocks includes a second fixed number of string-line (SL) blocks;

wherein each of the second fixed number of the SL blocks includes a third fixed number of page types; and

wherein each of the third fixed number of the page types includes a fourth fixed number of pages.

4. The data storage device of claim 1 , wherein, for a logical address of the respective open zone, a corresponding one of the one or more first L2P sub-tables has:

the physical address of the corresponding erase block; and

at least one of the corresponding word-line number; the corresponding string-line number; the corresponding page-type identifier; and the corresponding page offset.

5. The data storage device of claim 4 , wherein the compacting sub-table transfer includes the controller removing said at least one of the corresponding word-line number; the corresponding string-line number; the corresponding page-type identifier; and the corresponding page offset from the corresponding one of the one or more first L2P sub-tables.

6. The data storage device of claim 1 ,

wherein, for a logical address of the respective full zone, a corresponding one of the one or more second L2P sub-tables has the physical address of the corresponding erase block; and

wherein the controller is configured to obtain the corresponding sub-address combination by:

retrieving the physical address of the corresponding erase block from the corresponding one of the one or more second L2P sub-tables;

calculating the corresponding word-line number, the corresponding string-line number, the corresponding page-type identifier, and the corresponding page offset based on the host logical address; and

combining the physical address that is retrieved with the corresponding word-line number, the corresponding string-line number, the corresponding page-type identifier, and the corresponding page offset that are calculated.

7. The data storage device of claim 6 , wherein the controller is further configured to:

calculate an erase-block number corresponding to the logical address of the respective full zone; and

look up the physical address of the corresponding erase block in the corresponding one of the one or more second L2P sub-tables using the erase-block number that is calculated.

8. The data storage device of claim 6 , wherein the controller is configured to calculate the corresponding word-line number (WL num) based on a mathematical relationship expressed as:

WL num=((HLBA−O 1 )/(N 1 ×N 3 ×N 4 ))/N 5

where HLBA is the host logical address; N 1 is a number of erase blocks in a superblock of the plurality of superblocks; N 3 is a number of page types; N 4 is a number of pages per page type; N 5 is a number of string lines per word line; and O 1 is a fixed offset.

9. The data storage device of claim 6 , wherein the controller is configured to calculate the corresponding string-line number (SL num) based on a mathematical relationship expressed as:

SL num=((HLBA−O 1 )/(N 1 ×N 3 ×N 4 )) mod N 5

where HLBA is the host logical address; N 1 is a number of erase blocks in a superblock of the plurality of superblocks; N 3 is a number of page types; N 4 is a number of pages per page type; N 5 is a number of string lines per word line; and O 1 is a fixed offset.

10. The data storage device of claim 6 , wherein the controller is configured to calculate the corresponding page-type identifier (Page type ID) based on a mathematical relationship expressed as:

Page type ID=((HLBA−O 1 )/(N 3 ×N 4 )) mod N 3

where HLBA is the host logical address; N 3 is a number of page types; N 4 is a number of pages per page type; and O 1 is a fixed offset.

11. The data storage device of claim 6 , wherein the controller is configured to calculate the corresponding page offset (PO) based on a mathematical relationship expressed as:

PO=(HLBA−O 1 ) mod N 4

where HLBA is the host logical address; N 4 is a number of pages per page type; and O 1 is a fixed offset.

12. The data storage device of claim 1 ,

wherein, for a logical address of the respective full zone, a corresponding one of the one or more second L2P sub-tables only has the physical address of the corresponding erase block; and

wherein the de-compacting sub-table transfer includes:

the controller calculating the corresponding word-line number, the corresponding string-line number, the corresponding page-type identifier, and the corresponding page offset based on the logical address; and

the controller combining the physical address with the corresponding word-line number, the corresponding string-line number, the corresponding page-type identifier, and the corresponding page offset that are calculated.

13. An address-translation method for a data storage device, the method comprising:

mapping a plurality of superblocks of a nonvolatile memory of the data storage device to a plurality of zones, each of the plurality of zones being of a type requiring sequential write of host data, an erase block being a minimum erasable unit of the plurality of superblocks;

performing logical-to-physical (L2P) address translation using a controller coupled to the nonvolatile memory and further using a first L2P table and a second L2P table, the first L2P table including one or more first L2P sub-tables, each of the one or more first L2P sub-tables having a first granularity and assigned to a respective open zone of the plurality of zones, the second L2P table including one or more second L2P sub-tables, each of the one or more second L2P sub-tables having an erase-block granularity and assigned to a respective full zone of the plurality of zones, the first granularity being finer than the erase-block granularity;

performing, via the controller, a compacting sub-table transfer from the first L2P table to the second L2P table in response to detecting a finishing of the respective open zone; and

performing, via the controller, the L2P address translation of a host logical address by obtaining a corresponding sub-address combination including:

a physical address of a corresponding erase block;

a corresponding word-line number;

a corresponding string-line number;

a corresponding page-type identifier; and

a corresponding page offset.

14. The method of claim 13 ,

wherein a page is a minimum writable unit of the plurality of superblocks; and

wherein the first granularity is a page-level granularity.

15. The method of claim 13 , wherein said performing of the compacting sub-table transfer includes removing said at least one of the corresponding word-line number; the corresponding string-line number; the corresponding page-type identifier; and the corresponding page offset from the corresponding one of the one or more first L2P sub-tables.

16. The method of claim 13 ,

wherein, for a logical address of the respective full zone, a corresponding one of the one or more second L2P sub-tables only has the physical address of the corresponding erase block; and

wherein said performing the de-compacting sub-table transfer includes:

calculating the corresponding word-line number, the corresponding string-line number, the corresponding page-type identifier, and the corresponding page offset based on the logical address; and

combining the physical address with the corresponding word-line number, the corresponding string-line number, the corresponding page-type identifier, and the corresponding page offset that are calculated.

17. The method of claim 13 ,

wherein, for a logical address of the respective full zone, a corresponding one of the one or more second L2P sub-tables has the physical address of the corresponding erase block; and

wherein said performing the L2P address translation includes:

retrieving the physical address of the corresponding erase block from the corresponding one of the one or more second L2P sub-tables;

calculating the corresponding word-line number, the corresponding string-line number, the corresponding page-type identifier, and the corresponding page offset based on the host logical address; and

combining the physical address that is retrieved with the corresponding calculated word-line number, the corresponding string-line number, the corresponding page-type identifier, and the corresponding page offset that are calculated.

18. An apparatus, comprising:

means for mapping a plurality of superblocks of a nonvolatile memory to a plurality of zones, each of the plurality of zones being of a type requiring sequential write of host data therein, an erase block being a minimum erasable unit of the plurality of superblocks;

means for performing logical-to-physical (L2P) address translation using a first L2P table and a second L2P table, the first L2P table including one or more first L2P sub-tables, each of the one or more first L2P sub-tables having a first granularity and assigned to a respective open zone of the plurality of zones, the second L2P table including one or more second L2P sub-tables, each of the one or more second L2P sub-tables having an erase-block granularity and assigned to a respective full zone of the plurality of zones, the first granularity being finer than the erase-block granularity; and

means for performing a compacting sub-table transfer from the first L2P table to the second L2P table in response to detecting a finishing of the respective open zone,

wherein the means for performing L2P address translation are configured to perform the L2P address translation of a host logical address by obtaining a corresponding sub-address combination including:

a physical address of a corresponding erase block;

a corresponding word-line number;

a corresponding string-line number;

a corresponding page-type identifier; and

a corresponding page offset.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 31, 2022
From: MUTHYA NARAHARI, AVINASH; DASARATHAN, RAJTHILAK
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 060955/0534 →
Continuity (1)
Related Publication 20240069775A1 · Feb 29, 2024
References Cited (14)
US 8339865B2 · Lavan et al. · 2012 [cited by applicant]
US 10915475B2 · Dubey et al. · 2021 [cited by applicant]
US 10990526B1 · Lam et al. · 2021 [cited by applicant]
US 11055230B2 · Haswell · 2021 [cited by applicant]
US 11200162B2 · Helmick et al. · 2021 [cited by applicant]
US 20170153825A1 · Cho et al. · 2017 [cited by applicant]
US 20210294752A1 · Palmer · 2021 [cited by applicant]
US 20210374067A1 · Helmick et al. · 2021 [cited by applicant]
US 20220244869A1 · Kanteti · 2022 [cited by examiner]
US 20230075329A1 · Surianarayanan · 2023 [cited by examiner]
US 20230103355A1 · Surianarayanan · 2023 [cited by examiner]
US 20230168826A1 · Agarwal · 2023 [cited by examiner]
US 20230289078A1 · Wells · 2023 [cited by examiner]
NVM Express. Zoned Namespace Command Set Specification. Revision 1.1. May 18, 2021 (46 pages). [cited by applicant]