IP Library Granted Patent US 8,484,547
Granted Patent B2
US 8,484,547 · App. 13/728,944 · Granted Jul 9, 2013

System and method for reducing memory in a multi-channel parallel encoder system

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Quick Facts
Patent No.
US 8,484,547
App. No.
13/728,944
Filed
Dec 27, 2012
Granted
Jul 9, 2013
Kind
B2
Art Unit
2112
USPC
714/810
Abstract

A memory includes matrix data stored thereon for use by the plurality of encoders. An arbiter unit determines, for the plurality of encoders, respective times for the encoders to receive a portion of the matrix data stored in the shared memory, and facilitates providing a portion of the matrix data to the plurality of encoders according to the determined times for use in respective encoding operations.

Claims (52)

1. A system for encoding data in parallel using multiple encoders, comprising:

a shared memory including code-generating matrix data stored thereon;

a plurality of encoders operably connected to the shared memory, each encoder configured to encode a data payload to generate a codeword; and

an arbiter unit operably connected to the plurality of encoders and the shared memory, the arbiter unit configured to:

determine, for a respective encoder, a time for receiving a portion of the matrix data according to a timing schedule; and

provide the portion of the matrix data to the respective encoder for use in encoding operations at the determined time.

2. The system of claim 1 , wherein the arbiter unit provides the portion of the matrix data to each of the plurality of encoders by providing each respective encoder access to the shared memory according to the timing schedule.

3. The system of claim 1 , wherein the arbiter unit is further configured to:

receive, from the respective encoder, an indication that the encoder is ready to receive the portion of the matrix data, wherein the portion of the matrix data is provided at the determined time after the request.

4. The system of claim 1 , wherein the arbiter unit provides the portion of the matrix data by informing the respective encoder that the encoder may access the shared memory.

5. The system of claim 1 , wherein the portion of the matrix data is used by the encoder to generate one or more submatrices.

6. The system of claim 1 , wherein each encoder is configured to:

perform an encoding operation to encode a first payload portion of the data payload based on the provided portion of the matrix; and

request, on completion of the encoding operation, from the arbiter unit, a subsequent portion of the matrix to encode a subsequent portion of the data payload.

7. The system of claim 6 , wherein the encoding operation comprises:

encoding a first part of the first payload portion based on the provided portion of the matrix;

shifting the provided portion of the matrix to generate a shifted portion of the matrix;

encoding a different part of the first payload portion based on the shifted portion of the matrix; and

repeating the steps of shifting and encoding until the first payload portion is encoded.

8. The system of claim 1 , wherein the matrix comprises a plurality of circulants, and wherein the provided portion of the matrix comprises circulant data for facilitating the generation of at least a portion of the plurality of circulants.

9. The system of claim 5 , wherein the arbiter unit is further configured to:

maintain an index for each of the plurality of circulants;

maintain a current iteration of the index for each of the plurality of encoders;

receive an indication that an encoder is initiating an encoding of an un-encoded portion of the data payload; and

provide, on the indication, the circulant data based on a current iteration of the index for the encoder.

10. A method for encoding data using a plurality of encoders, the method comprising:

receiving a data payload;

determining a time for an encoder to receive a portion of matrix data stored at a shared memory location, the determined time being different than a time determined for at least one other encoder;

providing the encoder the portion of the matrix data according to the determined time;

encoding a portion of the data payload based on the received portion of the matrix, the encoding operating in parallel with an encoding initiated by at least one other encoder; and

repeating the steps of determining providing and encoding until the data payload is encoded.

11. The method of claim 10 , further comprising:

receiving an indication that the encoder is ready to receive the portion of the matrix data; and

informing the respective encoder that the encoder may access the shared memory.

12. The method of claim 10 , wherein the determined time is a clock cycle associated with a repeating timing schedule.

13. The method of claim 10 , wherein encoding the portion of the data payload comprises:

encoding a first subportion of the data payload based on the received portion of the matrix; and

iteratively shifting the received portion of the matrix to generate a shifted portion of the matrix, and encoding a different subportion of the data payload based on a shifted portion of the matrix, until the portion of the data payload is encoded.

14. The method of claim 10 , wherein the matrix comprises a plurality of circulants, and wherein the received portion of the matrix comprises one or more one-dimensional arrays corresponding to one or more respective circulants.

15. The method of claim 14 , wherein the step of encoding comprises:

iteratively shifting, at the encoder, the one or more one-dimensional arrays over a plurality of clock cycles to encode the portion of the data payload.

16. The method of claim 15 , wherein each bit of the data payload is encoded based on a bit value located at a corresponding bit position of the one or more one-dimensional arrays.

17. A system for encoding data using a plurality of encoders, the system comprising:

a shared memory including code-generating matrix data stored thereon;

an arbiter unit configured to facilitate access to the shared memory according to a timing schedule; and

a plurality of encoders operably connected to the arbiter unit and the shared memory, each encoder configured to:

receive a first set of elements based on the matrix data at a first time designated by the arbiter unit;

encode, on receiving the first set of elements, a portion of a data payload based on the first set of elements, the portion of the data payload being encoded in parallel with an encoding initiated by at least one other encoder; and

receive a second set of elements after the encoding of the portion of the data payload is completed, at a second time designated by the arbiter unit.

18. The system of claim 17 , wherein the first set of elements comprises a one-dimensional array of elements spanning a plurality of submatrices.

19. The system of claim 17 , wherein the encoding initiated by the at least one other encoder is based on the first set of elements.

20. The system of claim 17 , wherein the first set of elements comprises multiple one-dimensional arrays, each corresponding to one of a plurality of submatrices at identical respective positions within the submatrices, and wherein the portion of the data payload includes a plurality of bits, a bit being encoded based on bit values located at corresponding positions within the multiple one-dimensional arrays.

Assignments (12)
SECURITY AGREEMENT (SUPPLEMENTAL) Recorded Nov 14, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 069411/0208 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 11, 2024
From: SANDISK TECHNOLOGIES, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 069168/0273 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 16, 2018
From: HGST TECHNOLOGIES SANTA ANA, INC.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046174/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2016
From: JAKKA, BHASKER R.; DASH, DILLIP K.
To: STEC, INC.
Reel/Frame 039488/0869 →
CHANGE OF NAME Recorded Jul 1, 2015
From: STEC, INC.
To: HGST TECHNOLOGIES SANTA ANA, INC.
Reel/Frame 036042/0390 →