Data storage device with multi-commands
Providing constant fixed commands to memory dies within a data storage device may result in hardware and firmware overheads impacting the performance at a flash interface module (FIM) because the FIM has to handle both the constant fixed commands and the overheads associated with the constant fixed commands. To avoid the impact on performance at the FIM, multiple fixed commands may be combined into individual multi-commands that may be provided to the memory dies. The use of multi-commands reduces hardware and firmware overheads at the FIM relative to the constant fixed commands, which improves performance of the data storage device because the saturation of the FIM is decreased.
1. A data storage device comprising:
a memory including a plurality of memory dies, the memory configured to:
read data from the plurality of memory dies using one or more multi-commands, and
perform asynchronous independent plane reads (AIPR) on the plurality of memory dies;
a data storage controller including a flash interface module (FIM) configured to communicate with the memory using a bus and channel transfers on the bus,
wherein the channel transfers include a plurality of data transfers of the data that is read and a plurality of overheads associated with performing the AIPR on the plurality of memory dies, and
wherein a number of the plurality of overheads is less than a number of the plurality of data transfers; and
circuitry configured to:
determine whether a current parallelism at the plurality of memory dies is enough to saturate the FIM,
determine whether new commands are issued after a time window, and
hold the new commands for a period of time in response to determining that the current parallelism at the plurality of memory dies is enough to saturate the FIM and in response to determining that the new commands are issued after the time window.
2. The data storage device of claim 1 , wherein two or more of the plurality of data transfers and one of the plurality of overheads are associated with one of the one or more multi-commands.
3. The data storage device of claim 1 ,
wherein the circuitry is further configured to:
control issuance of a plurality of commands to the plurality of memory dies, and
maintain a time window to issue new commands on a different plane.
4. The data storage device of claim 3 , wherein, to control issuance of the plurality of commands to the plurality of memory dies, the circuitry is further configured to track all of the plurality of commands simultaneously.
5. The data storage device of claim 3 , wherein, to control issuance of the plurality of commands to the plurality of memory dies, the circuitry is further configured to
determine whether a saturation level of the FIM is one of undersaturated, saturated, or oversaturated, and
control the issuance of the plurality of commands to the plurality of memory dies based on the determination of whether the saturation level of the FIM is the one of the undersaturated, the saturated, or the oversaturated.
6. The data storage device of claim 1 , further comprising:
circuitry configured to:
dynamically determine a parallelism of the plurality of memory dies that can saturate the FIM based on a speed of the bus, a total number of outstanding commands available at the FIM, and a total number of commands available in the data storage device, and
set the parallelism that is dynamically determined.
7. A method comprising:
reading, with a memory, data from a plurality of memory dies using one or more multi-commands;
performing asynchronous independent plane reads (AIPR) on the plurality of memory dies;
communicating the data that is read to a flash interface module (FIM) with a bus and channel transfers on the bus,
wherein the channel transfers include a plurality of data transfers of the data that is read and a plurality of overheads associated with performing the AIPR on the plurality of memory dies, and
wherein a number of the plurality of overheads is less than a number of the plurality of data transfers;
determining whether a current parallelism at the plurality of memory dies is enough to saturate the FIM;
determining whether new commands are issued after a time window; and
holding the new commands for a period of time in response to determining that the current parallelism at the plurality of memory dies is enough to saturate the FIM and in response to determining that the new commands are issued after the time window.
8. The method of claim 7 , wherein two or more of the plurality of data transfers and one of the plurality of overheads are associated with one of the one or more multi-commands.
9. The method of claim 7 , further comprising:
controlling issuance of a plurality of commands to the plurality of memory dies; and
maintaining a time window to issue new commands on a different plane.
10. The method of claim 9 , wherein controlling the issuance of the plurality of commands to the plurality of memory dies further includes tracking all of the plurality of commands simultaneously.
11. The method of claim 9 , wherein controlling the issuance of the plurality of commands to the plurality of memory dies further includes:
determining whether a saturation level of the FIM is one of undersaturated, saturated, or oversaturated, and
controlling the issuance of the plurality of commands to the plurality of memory dies based on the determination of whether the saturation level of the FIM is the one of the undersaturated, the saturated, or the oversaturated.
12. The method of claim 7 , further comprising:
dynamically determining a parallelism of the plurality of memory dies that can saturate the FIM based on a speed of the bus, a total number of outstanding commands available at the FIM, and a total number of commands available in a data storage device; and
setting the parallelism that is dynamically determined.
13. An apparatus comprising:
means for reading data from a plurality of memory dies using one or more multi-commands;
means for performing asynchronous independent plane reads (AIPR) on the plurality of memory dies;
means for communicating the data that is read to a flash interface module (FIM) with a bus and channel transfers on the bus,
wherein the channel transfers include a plurality of data transfers of the data that is read and a plurality of overheads associated with performing the AIPR on the plurality of memory dies, and
wherein a number of the plurality of overheads is less than a number of the plurality of data transfers;
determining whether a current parallelism at the plurality of memory dies is enough to saturate the FIM;
determining whether new commands are issued after a time window; and
holding the new commands for a period of time in response to determining that the current parallelism at the plurality of memory dies is enough to saturate the FIM and in response to determining that the new commands are issued after the time window.
14. The apparatus of claim 13 , wherein two or more of the plurality of data transfers and one of the plurality of overheads are associated with one of the one or more multi-commands.
15. The apparatus of claim 13 , further comprising:
controlling issuance of a plurality of commands to the plurality of memory dies; and
maintaining a time window to issue new commands on a different plane.
16. The apparatus of claim 13 , further comprising:
means for dynamically determining a parallelism of the plurality of memory dies that can saturate the FIM based on a speed of the bus, a total number of outstanding commands available at the FIM, and a total number of commands available in a data storage device; and
means for setting the parallelism that is dynamically determined.
17. An apparatus comprising:
means for reading data from a plurality of memory dies using one or more multi-commands;
means for performing asynchronous independent plane reads (AIPR) on the plurality of memory dies;
means for communicating the data that is read to a flash interface module (FIM) with a bus and channel transfers on the bus,
wherein the channel transfers include a plurality of data transfers of the data that is read and a plurality of overheads associated with performing the AIPR on the plurality of memory dies, and
wherein a number of the plurality of overheads is less than a number of the plurality of data transfers;
controlling issuance of a plurality of commands to the plurality of memory dies; and
maintaining a time window to issue new commands on a different plane,
wherein controlling the issuance of the plurality of commands to the plurality of memory dies further includes:
determining whether a saturation level of the FIM is one of undersaturated, saturated, or oversaturated, and
controlling the issuance of the plurality of commands to the plurality of memory dies based on the determination of whether the saturation level of the FIM is the one of the undersaturated, the saturated, or the oversaturated.