Enabling high speed command address interface for random read
A memory device includes a memory controller to transmit or receive input/output (“I/O”) data via an I/O signal, as well as transmit command data, address data, or parameter data via another signal in parallel with transmitting or receiving the I/O data. The memory device also includes a memory module communicably coupled to the memory controller. The memory module receives the command data, address data, or parameter data from the memory controller to perform an operation.
1. A memory device comprising:
a memory controller having programmed instructions to:
transmit or receive input/output (“I/O”) data via an I/O signal through one or more I/O pads;
transmit command data, address data, or parameter data serially via another signal through another pad in parallel with transmitting or receiving the I/O data through the one or more I/O pads; and
a memory module communicably coupled to the memory controller, wherein the memory module is configured to receive the command data, address data, or parameter data from the memory controller and convert the serial command data, address data, or parameter data to parallel data to perform an operation.
2. The memory device of claim 1 , wherein the memory controller transmits the command data, the address data, or the parameter data to the memory module via a data latch enable (“DLE”) signal.
3. The memory device of claim 2 , wherein the memory controller further transmits:
a command latch enable (“CLE”) signal; and
an address latch enable (“ALE”) signal,
wherein the CLE signal and the ALE signal are control signals indicative of whether the DLE signal is transmitting the command data, the address data, or the parameter data.
4. The memory device of claim 1 , wherein:
the one or more I/O pads consist of eight first I/O pads and the other pad is a first DLE pad for transmitting the DLE signal to the memory module; and
the memory module comprises a second DLE pad for receiving the DLE signal from the memory controller and eight second I/O pads for receiving or transmitting the I/O signal.
5. The memory device of claim 1 , wherein the memory controller is configured to send the command data, the address data, or the parameter data serially in 1-bit increments.
6. The memory device of claim 5 , wherein:
the memory module comprises a counter to count a number of pulses of a clock signal received from the memory controller, each of the 1-bit increments being sent by the memory controller with respect to a pulse of the clock signal;
the counter generates a transition signal upon counting the number of pulses; and
the memory module converts the serially received 1 -bit increments into parallel data upon receiving a modified clock signal generated based upon the transition signal.
7. The memory device of claim 1 , wherein:
the operation comprises a first read operation and a second read operation; and
the memory controller receives the I/O data from the memory module via the I/O signal for the first read operation in parallel with sending a command for the second read operation to the memory module.
8. The memory device of claim 1 , wherein:
the memory controller transmits the command data, the address data, or the parameter data via a command latch enable (“CLE”) signal and an address latch enable (“ALE”) signal; and
the CLE signal comprises a CLE header and the ALE signal comprises an ALE header, the combination of the CLE header and the ALE header indicative of whether the CLE signal and the ALE signal are transmitting the command data, the address data, or the parameter data.
9. The memory device of claim 8 , wherein the CLE signal and the ALE signal transmit the command data when the CLE header is asserted and the ALE header is disabled.
10. The memory device of claim 8 , wherein the CLE signal and the ALE signal transmit the address data when the ALE header is asserted and the CLE header is disabled.
11. The memory device of claim 8 , wherein the CLE signal and the ALE signal transmit the parameter data when the CLE header is disabled and the ALE header is disabled.
12. The memory device of claim 8 , wherein the CLE signal and the ALE signal transmit the CLE header and the ALE header, respectively, before transmitting the command data, the address data, or the parameter data.
13. The memory device of claim 8 , wherein the CLE signal and the ALE signal transmit the command data, the address data, or the parameter data serially in 1-bit increments.
14. A non-transitory computer-readable media having computer-readable instructions stored thereon that when executed by a memory module cause the memory module to perform a process comprising:
receiving a first read command from a memory controller;
transferring data to the memory controller as parallel data, via a plurality of data pads, in response to the first read command;
receiving a second read command from the memory controller as serial data, via another pad that is separate from the plurality of data pads, in parallel with transferring the data to the memory controller; and
converting the serial data to parallel data of the second read command.
15. The non-transitory computer-readable media of claim 14 , wherein receiving the first read command and the second read command comprises:
receiving a clock signal from the memory controller;
receiving a data latch enable (“DLE”) signal from the memory controller, wherein the DLE signal transmits command data, address data, or parameter data from the memory controller serially in 1-bit increments with respect to a pulse of the clock signal;
receiving a command latch enable (“CLE”) signal and an address latch enable (“ALE”) signal indicating whether the DLE signal is transmitting the command data, the address data, or the parameter data;
generating a modified clock signal upon counting the number of pulses; and
converting the serially received 1-bit increments into parallel data upon receiving the modified clock.
16. The non-transitory computer-readable media of claim 15 , further comprising:
converting the CLE signal into a derivative CLE signal, wherein a logic level of the derivative CLE signal is same as the logic level of the CLE signal; and
converting the ALE signal into a derivative ALE signal, wherein the logic level of the derivative ALE signal is same as the logic level of the ALE signal.
17. The non-transitory computer-readable media of claim 14 , wherein receiving the first read command and the second read command comprises:
receiving a clock signal from the memory controller;
decoding a header of a command latch enable (“CLE”) signal and an address latch enable (“ALE”) signal received from the memory controller to determine whether the CLE signal and the ALE signal are transmitting command data, address data, or parameter data after the header, and wherein the CLE signal and the ALE signal transmit the command data, the address data, or the parameter data serially in 1-bit increments with respect to a pulse of the clock signal;
generating a modified clock signal upon counting the number of pulses; and
converting the serially received 1-bit increments into parallel data upon receiving the modified clock signal.
18. A non-transitory computer-readable media having computer-readable instructions stored thereon that when executed by a memory controller cause the memory controller to perform a process comprising:
sending a clock signal to a memory module;
sending command data, address data, or parameter data via a data latch enable (“DLE”) signal to the memory module with respect to the clock signal, wherein the memory controller sends at least 1 bit of the command data, address data, or parameter data during each pulse of the clock signal;
sending a command latch enable (“CLE”) signal and an address latch enable (“ALE”) signal indicating that the command data, the address data, or the parameter data is being sent; and
receiving input/output (“I/O”) data from the memory module via an I/O signal in parallel with sending the command data, the address data, or the parameter data to the memory module.
19. The non-transitory computer-readable media of claim 18 , wherein sending the command data, the address data, or the parameter data via the data latch enable (“DLE”) signal includes transmitting the command data, the address data, or the parameter data to the memory module serially in 1-bit increments.
20. The non-transitory computer-readable media of claim 18 , wherein the process further comprises:
sending a header in the CLE signal and the ALE signal, wherein the header is indicative of whether the CLE signal and the ALE signal are transmitting the command data, the address data, or the parameter data after the header; and
receiving the I/O data via an I/O signal in parallel.