Automated fast path processing
Processing commands received from a host computing device by a storage device can require a large amount of processing overhead. This demand for ever greater processing power increases as the size of storage devices increase. Traditional methods have added an increasing number of processors or CPUs to handle these requirements. However, by utilizing a fast path accelerated processing pipeline, additional processors may not be necessary. An accelerated processing pipeline can be configured to bypass one or more steps that are required by non-priority processing pipelines. Each received command can be parsed to determine if it is suitable for accelerated processing. The command can be required to access data in a limited region of the memory device, or to have any data necessary to process the command already in a cache memory. Upon completion of verifications, commands can be placed in a priority queue that is processed before a non-priority queue.
1. A device comprising:
a processor; a memory array comprising a plurality of memory devices; and
an accelerated processing logic configured to:
receive incoming commands;
parse the received incoming commands;
pass one or more parsed commands to a parallel accelerated processing pipeline, wherein the parallel accelerated processing pipeline comprising a first accelerated processing memory in a front-end and flash translation layer and a second accelerated processing memory in a physical storage layer;
perform, within the parallel accelerated processing pipeline, one or more verifications on the parsed command, to determine its eligibility for prioritized die-specific processing, wherein the one or more verifications comprise at least determining if data associated with the parsed command is accessible from one or more cache memories;
determine a die associated with the parsed command;
add, upon passing the one or more verifications, the parsed command into a priority queue among the one or more priority queues wherein the priority queue is associated with the determined die,
arbitrate the parsed command against one or more non-priority queues; and process the parsed command in the priority queue before commands within a non-priority queue.
2. The device of claim 1 , wherein the incoming commands are received from a host computing device.
3. The device of claim 2 , wherein incoming commands are read commands configured to retrieve data stored within the memory array of the device.
4. The device of claim 3 , wherein the accelerated processing logic if further configured to parse the received incoming commands to determine if the received incoming commands are suitable for accelerated processing.
5. The device of claim 4 , wherein the suitability of the parsed command is determined by a type of command received.
6. The device of claim 5 , wherein the type of command received is a read command with a size below a predetermined threshold.
7. The device of claim 6 , wherein the predetermined threshold is sixteen kilobytes.
8. The device of claim 5 , wherein the plurality of memory devices are located within one or more dies.
9. The device of claim 6 , wherein the read command is associated with memory devices located on the same die within the memory array.
10. The device of claim 1 , wherein the accelerated processing logic is further configured to determine the number of commands currently in the parallel accelerated processing pipeline prior to passing in additional commands.
11. The device of claim 10 , wherein, upon determination that the number of commands in the parallel accelerated processing pipeline is above a predetermined threshold, passing the one or more parsed commands to a non-accelerated processing pipeline.
12. The device of claim 1 , wherein, upon failing the one or more verifications, the command is passed to a non-accelerated processing pipeline.
13. The device of claim 12 , wherein a verification fails if data associated with the command is not retrievable from a cached memory.
14. A method for accelerated storage device processing, comprising:
receiving incoming commands from a host computing device;
determining if the received commands are suitable for accelerated processing;
passing the suitable commands to a parallel accelerated processing pipeline, wherein the parallel accelerated processing pipeline comprising a first accelerated processing memory in a front-end and flash translation layer and a second accelerated processing memory in a physical storage layer;
performing, within the parallel accelerated processing pipeline, one or more verifications on the parsed command, to determine its eligibility for prioritized die-specific processing, wherein the one or more verifications comprise at least determining if associated data is accessible from one or more cache memories;
determining a die associated with the at least one suitable command;
adding, upon passing the one or more verifications, the at least one suitable command into a priority queue associated with the determine die to read data from a memory array,
wherein commands in the priority queue will be processed before commands within a non-priority queue; and
arbitrating the one or more suitable commands within the priority queue against the non-priority queues.
15. The method of claim 14 , wherein suitable commands are configured to be random read commands that are smaller than a predetermined size.
16. The method of claim 14 , wherein suitable commands are configured to read data from a plurality of memory devices located within the same die within a memory array of the device.
17. The method of claim 15 , wherein the one or more verifications comprise locating data associated with the command within the one or more cache memories.
18. A device comprising:
a processor;
a memory array comprising a plurality of memory devices; and
an accelerated processing logic configured to:
establish a non-accelerated processing pipeline;
receive incoming commands;
parse the received incoming commands;
establish, upon determination that a parsed command is suitable for accelerated processing, a parallel accelerated processing pipeline, wherein the parallel accelerates processing pipeline comprising a first accelerated processing memory in a front-end and flash translation layer and a second accelerated processing memory in a physical storage layer;
pass the suitable command to the parallel accelerated processing pipeline;
perform, within the parallel accelerated processing pipeline, one or more verifications on the parsed command, to determine its eligibility for prioritized die-specific processing, wherein the one or more verifications comprise at least determining if data associated with the suitable command is accessible from one or more cache memories;
determine a die associated with the suitable command;
add, upon passing the one or more verifications, the command into a priority queue associated with the determined die, wherein commands in the priority queue will be processed before commands within a non-priority queue; and
arbitrate a read command within the priority queue.
19. The device of claim 18 , wherein the priority queue is dynamically generated upon the establishment of the parallel accelerated processing pipeline by changing one or more properties associated with a non-priority queue such that it is subsequently processed as a priority queue.
20. The device of claim 19 , wherein, upon the queue of the parallel accelerated processing pipeline becoming empty, any resources utilized to establish the accelerated processing pipeline and priority queues are released to the non-accelerated processing pipeline and non-priority queues.