Data storage device and method for dynamic logical page write ordering
In some situations, the programming of one memory die can be suspended in favor of the programming of another memory die. This can lead to a delay in certain programming operations. To avoid this problem, a data storage device can perform dynamic logical page write ordering by determining an availability of each memory die of a plurality of memory dies and changing a programing order of the plurality of memory dies in response to the determined availability.
1. A data storage device comprising:
a memory comprising a plurality of memory dies; and
a processor coupled with the memory and configured to:
suspend a triple-level cell (TLC) write for a single-level cell (SLC) parity write;
determine an availability of each memory die of the plurality of memory dies; and
change a programing order of the plurality of memory dies for a subsequent TLC write in response to the determined availability.
2. The data storage device of claim 1 , wherein the availability of at least one memory die is based on queue per die (QPD) metric.
3. The data storage device of claim 1 , wherein the processor is further configured initiate a write in one of the plurality of memory dies determined to be available.
4. The data storage device of claim 3 , wherein the write causes garbage collection data to be written.
5. The data storage device of claim 3 , wherein the write causes host data to be written.
6. The data storage device of claim 1 , wherein the processor is further configured to modify a write pattern for every write.
7. The data storage device of claim 1 , wherein the processor is further configured to align written data to parity writes in a parity block.
8. The data storage device of claim 1 , wherein the processor is further configured to suspend writing of first data in favor of writing second data.
9. The data storage device of claim 1 , wherein at least one of the plurality of memory dies comprises a three-dimensional memory array.
10. The data storage device of claim 1 , wherein:
determining the availability of each memory die comprises determining which memory die of the plurality of memory dies will not be suspended in the subsequent TLC write; and
changing the programing order comprises selecting the memory die that will not be suspended in the subsequent TLC write as a last-programmed memory die for the subsequent TLC write.
11. In a data storage device comprising a memory comprising a plurality of memory dies, a method comprising:
suspending a triple-level cell (TLC) write for a single-level cell (SLC) parity write;
determining an availability of each memory die of the plurality of memory dies; and
changing a programing order of the plurality of memory dies for a subsequent TLC write in response to the determined availability.
12. The method of claim 11 , wherein the availability of at least one memory die is based on queue per die (QPD) metric.
13. The method of claim 11 , wherein the controller is further configured initiate a write in one of the plurality of memory dies determined to be available.
14. The method of claim 13 , wherein the write causes garbage collection data to be written.
15. The method of claim 13 , wherein the write causes host data to be written.
16. The method of claim 11 , further comprising modifying a write pattern for every write.
17. The method of claim 11 , further comprising aligning written data to parity writes in a parity block.
18. The method of claim 11 , further comprising suspending writing of first data in favor of writing second data.
19. The method of claim 11 , wherein:
determining the availability of each memory die comprises determining which memory die of the plurality of memory dies will not be suspended in the subsequent TLC write; and
changing the programing order comprises selecting the memory die that will not be suspended in the subsequent TLC write as a last-programmed memory die for the subsequent TLC write.
20. A data storage device comprising:
a memory comprising a plurality of memory dies;
means for suspending a triple-level cell (TLC) write for a single-level cell (SLC) parity write;
means for determining an availability of each memory die of the plurality of memory dies; and
means for changing a programing order of the plurality of memory dies for a subsequent TLC write in response to the determined availability.