IP Library Granted Patent US 11,960,758
Granted Patent B2
US 11,960,758 · App. 17/714,328 · Granted Apr 16, 2024

Storage system and folding method for enhanced performance

Inventors: Bhanushankar Doni Gurudath (Bangalore, IN); Harish Gajula (Bangalore, IN)
Assignee: Western Digital Technologies, Inc.
G06F3/0655G06F3/0604G06F3/0679
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Quick Facts
Patent No.
US 11,960,758
App. No.
17/714,328
Granted
Apr 16, 2024
Kind
B2
Abstract

Rather than use one long folding operation to fold data from single-level cell (SLC) blocks into a multi-level cell (MLC) block, a storage system uses a multi-stage folding operation. By breaking up the folding process into stages, SLC blocks involved in an earlier stage can be released prior to a subsequent stage being performed. This can increase performance of the storage system by releasing SLC source blocks sooner and reducing an SLC block budget requirement.

Claims (50)

1. A storage system comprising:

a memory comprising a plurality of single-level cell (SLC) blocks and a multi-level cell (MLC) block; and

a controller coupled to the memory and configured to fold data stored in the plurality of SLC blocks into the MLC block using a multi-stage process;

wherein the controller is further configured to:

perform a first stage of the multi-stage process, wherein in the first stage, a first subset of the plurality of SLC blocks is folded into a first subset of pages of the MLC block; and

in response to successful completion of the first stage of the multi-stage process:

perform a second stage of the multi-stage process, wherein in the second stage, a second subset of the plurality of SLC blocks is folded into a second subset of pages of the MLC block, wherein the second stage is performed without reading data written in the first stage and writing it back in the second stage; and

release the first subset of the plurality of SLC blocks between the first and second stages.

2. The storage system of claim 1 , wherein the controller is further configured to perform the first stage irrespective of validity of data in the first subset of SLC blocks.

3. The storage system of claim 1 , wherein the first and second stages are performed sequentially at different times and not in parallel.

4. The storage system of claim 1 , wherein:

the MLC block comprises a quad-level cell (QLC) block;

in the first stage, two SLC blocks are folded into lower and middle pages of the QLC block; and

in the second stage, two other SLC blocks are folded into upper and top pages of the QLC block.

5. The storage system of claim 1 , wherein:

the MLC block comprises a quad-level cell (QLC) block; and

in the first stage, a first SLC block is written into lower and middle pages of the QLC block, then released before a second SLC block is written into the lower and middle pages of the QLC block.

6. The storage system of claim 5 , wherein:

in the second stage, a third SLC block is written into upper and top pages of the QLC block, then released before a fourth SLC block is written into the upper and top pages of the QLC block.

7. The storage system of claim 1 , wherein:

the MLC block comprises a quad-level cell (QLC) block; and

in the second stage, one SLC block is written into upper and top pages of the QLC block, then released before another SLC block is written into the upper and top pages of the QLC block.

8. The storage system of claim 1 , wherein the controller is further configured to fold the data in response to a number of available SLC blocks in the memory being below a threshold.

9. The storage system of claim 1 , wherein the controller is further configured to verify that the first subset of the plurality of SLC blocks was successfully written in the first subset of pages of the MLC block before releasing the first subset of the plurality of SLC blocks.

10. The storage system of claim 1 , wherein the controller is further configured to release the second subset of the plurality of SLC blocks after the second stage.

11. The storage system of claim 1 , wherein the memory comprises a three-dimensional memory.

12. In a storage system comprising a memory comprising a plurality of single-level cell (SLC) blocks and a quad-level cell (QLC) block, a method comprising:

determining how many SLC blocks are available for folding; and

in response to determining that two SLC blocks are available for folding:

determining whether lower and middle pages of the QLC block have been programmed;

in response to determining that the lower and middle pages of the QLC block have not been programmed;

programming the lower and middle pages of the QLC block with the two SLC blocks; and then

in response to the lower and middle pages of the QLC block being programmed successfully:

releasing the two SLC blocks; and then programming upper and top pages of the QLC block; and

in response to determining that the lower and middle pages of the QLC block have been programmed, programming the upper and top pages of the QLC block with the two SLC blocks.

13. The method of claim 12 , wherein the upper and top pages of the QLC block are programmed without reading data written in the lower and middle pages of the QLC block and using that data in programming the upper and top pages of the QLC block.

14. The method of claim 12 , wherein the lower and middle pages of the QLC block are programmed with the two SLC blocks irrespective of a validity of data stored in the two SLC blocks.

15. The method of claim 12 , further comprising:

in response to determining that four SLC blocks are available for folding, fold the four SLC blocks into the QLC block.

16. The method of claim 12 , wherein determining how many SLC blocks are available for folding is performed in response to determining that a number of available SLC blocks in the memory is below a threshold.

17. The method of claim 12 , wherein the two SLC blocks are released in response to verifying that the lower and middle pages have been successfully written.

18. The storage system of claim 17 , further comprising using an enhanced post-write read (EPWR) operation to verify that the lower and middle pages have been successfully written.

19. The method of claim 12 , further comprising releasing the two SLC blocks after the upper and top pages have been programmed.

20. A storage system comprising:

a memory comprising a plurality of single-level cell (SLC) blocks and a multi-level cell (MLC) block; and

means for folding data stored in the plurality of SLC blocks into the MLC block using a multi-stage process;

wherein:

in a first stage of the multi-stage process, a first subset of the plurality of SLC blocks is folded into a first subset of pages of the MLC block;

in a second stage of the multi-stage process, which is performed in response to successful completion of the first stage, a second subset of the plurality of SLC blocks is folded into a second subset of pages of the MLC block, wherein the second stage is performed without reading data written in the first stage and writing it back in the second stage; and

the first subset of the plurality of SLC blocks is released between the first and second stages.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 6, 2022
From: GURUDATH, BHANUSHANKAR DONI; GAJULA, HARISH
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059515/0436 →
Continuity (1)
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