Asynchronous FIFO for power-domain crossing
In one aspect of the disclosure, a circuit includes an AFIFO in a first power domain coupled to a first data bus and configured to store up to N data words corresponding to N respective AFIFO outputs. A multiplexer (MUX) in the first power domain selectively coupled to the N AFIFO outputs may transfer, upon receiving a MUX input, less than N words onto a fixed interface. Read logic in a second power domain may send an asynchronous read pointer to the MUX input and may transfer the words output from the fixed interface to a second data bus. Write logic in the first power domain may send asynchronous write pointers to the AFIFO for tracking data writes thereto and to the read logic to determine values of the read pointer.
1. A circuit, comprising:
an asynchronous first-in first-out buffer (AFIFO) in a first power domain coupled to a first data bus and configured to store N data words corresponding to N respective AFIFO outputs;
a second data bus crossing an interface from the first power domain to a second power domain;
a multiplexer (MUX) coupled to the N AFIFO outputs and configured to transfer data over the second data bus of less than N words upon receiving a MUX input;
a synchronizer in the first power domain configured to provide the MUX input; and
read logic in the second power domain to send an asynchronous read pointer across the interface to the synchronizer, and to receive the data,
wherein a width of the second data bus is independent of a depth N of the AFIFO and dependent on a number of stages in the synchronizer.
2. The circuit of claim 1 , further comprising:
a second synchronizer in the second power domain configured to allow the read logic to determine when new data is present in the AFIFO; and
write logic in the first power domain configured to send an asynchronous write pointer to:
the AFIFO for tracking data writes to the AFIFO, and
the second synchronizer across the interface.
3. The circuit of claim 1 , further comprising:
a plurality of cells coupled to the second data bus and arranged between the MUX and the read logic and configured to modify the less than N words on the second data bus to be compatible with a power supply in the second power domain.
4. The circuit of claim 3 , wherein the cells comprise at least one of isolation cells, level-shifter cells or register retention cells.
5. The circuit of claim 1 , wherein the synchronizer is a plurality of flip-flops.
6. The circuit of claim 1 , further comprising:
a second synchronizer in the second power domain configured to allow the read logic to determine when new data is present in the AFIFO, wherein the second synchronizer is a plurality of flip-flops.
7. The circuit of claim 1 , further comprising:
a converter configured to decode a gray-encoded read pointer, wherein the asynchronous read pointer is the gray-encoded read pointer, and the synchronizer is coupled to the converter in the first power domain.
8. The circuit of claim 1 , wherein the width of the second data bus further depends on a ratio of a read-to-write frequency of the AFIFO.
9. The circuit of claim 1 , further comprising:
a second synchronizer in the second power domain configured to allow the read logic to determine when new data is present in the AFIFO; and
write logic in the first power domain configured to send an asynchronous write pointer to:
the AFIFO for tracking data writes to the AFIFO, and
the second synchronizer across the interface;
wherein a rate of transferring the data through the MUX is determined such that the asynchronous read pointer and the asynchronous write pointer have predictable values in the first power domain and the second power domain, respectively, after passing through the synchronizer and the second synchronizer, respectively.
10. The circuit of claim 1 , further comprising:
a second synchronizer in the second power domain configured to allow the read logic to determine when new data is present in the AFIFO;
wherein the synchronizer and the second synchronizer are respectively configured to operate on both a rising edge and a falling edge of a respective clock input to allow multiple read operations within a clock cycle.
11. The circuit of claim 1 , further comprising:
a second synchronizer in the second power domain configured to allow the read logic to determine when new data is present in the AFIFO;
wherein at least one of the synchronizer and the second synchronizer includes an edge detector circuit configured to output a pulse upon detecting at least one of a rising edge or a falling edge of a respective clock input.
12. The circuit of claim 1 , wherein the second data bus comprises a multiple-word interface from which read operations via the MUX input are configured to occur, when data is available, for alternate cycles of a clock input received at the read logic.
13. The circuit of claim 1 , wherein circuit elements in the first power domain are configured to be supplied by a first power source that is different from, or identical to, a second power source configured to supply circuit elements in the second domain.
14. The circuit of claim 1 , wherein the first power domain and the second power domain, while configured as asynchronous, share an identical clock source.
15. The circuit of claim 1 , wherein the read logic is further configured to use a read clock input to sequentially latch the data from the second data bus onto a third data bus, wherein the third data bus has a width that is smaller than the width of the second data bus.
16. A storage controller, comprising:
an asynchronous first-in first-out buffer (AFIFO) in a first power domain coupled to a first data bus and configured to store N data words corresponding to N respective AFIFO outputs;
a fixed interface between the first power domain and a second power domain;
a multiplexer (MUX) coupled to the N AFIFO outputs and configured to asynchronously transfer, upon receiving a MUX input, less than N words onto the fixed interface;
a synchronizer in the first power domain configured to provide the MUX input; and
read logic in the second power domain configured to send an asynchronous read pointer to the synchronizer and to send the less than N words transferred onto the fixed interface to a second data bus,
wherein a width of the fixed interface is independent of a depth N of the AFIFO and dependent on a number of stages in the synchronizer.
17. The storage controller of claim 16 , further comprising:
a plurality of cells coupled to the fixed interface and arranged between the MUX and the read logic and configured to modify the less than N words on the fixed interface to be compatible with a power supply in the second power domain.
18. The storage controller of claim 16 , further comprising write logic in the first power domain configured to send asynchronous write pointers to:
the AFIFO for tracking data writes to the AFIFO, and
the read logic to determine values of the asynchronous read pointer.
19. The storage controller of claim 16 , wherein the synchronizer is a plurality of flip-flops.
20. A storage controller, comprising:
an asynchronous first-in first-out buffer (AFIFO) in a first power domain coupled to a first data bus and configured to store N data words corresponding to N respective AFIFO outputs;
a fixed interface between the first power domain and a second power domain;
a multiplexer (MUX) in the first power domain coupled to the N AFIFO outputs and configured to transfer, upon receiving a MUX input, less than N words onto the fixed interface;
a first synchronizer in the first power domain configured to provide the MUX input;
read logic in the second power domain for sending an asynchronous read pointer to the first synchronizer and for sending the less than N words transferred to the fixed interface to a second data bus;
a second synchronizer in the second power domain configured to provide a synchronized write pointer to the read logic; and
write logic in the first power domain for sending an asynchronous write pointer to the AFIFO for tracking data writes and to the second synchronizer,
wherein a width of the fixed interface is independent of a depth N of the AFIFO and dependent on a number of stages in the first synchronizer.