IP Library Granted Patent US 11,327,684
Granted Patent B2
US 11,327,684 · App. 16/874,101 · Granted May 10, 2022

Storage system and method for host memory access

Inventors: Rotem Sela (Haifa, IL); Amir Shaharabany (Kochav Yair, IL); Eliad Adi Klein (Sunnyvale, CA)
Assignee: Western Digital Technologies, Inc.
G06F3/0659G06F3/0619G06F3/0653G06F3/0683G06F9/30189G06F11/1435
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Quick Facts
Patent No.
US 11,327,684
App. No.
16/874,101
Granted
May 10, 2022
Kind
B2
Abstract

A storage system and method for host memory access are provided. In one embodiment, a storage system is configured to receive a write command from a host that is recognized by the storage system as a read host memory command and receive a read command from the host that is recognized by the storage system as a write host memory command. This provides a communication channel that allows the storage system to access the host memory. The storage system can use the host memory as a backup write cache and/or to stream data of different types stored in different areas of the host memory. Hibernation can be avoided, and timeout delays can be ignored. Other embodiments are provided.

Claims (41)

1. A storage system comprising:

a storage system memory; and

a controller configured to communicate with the storage system memory and with a host comprising a host memory, wherein the controller is further configured to:

receive a write command from the host that is recognized by the storage system as a read host memory command and establishes a read channel between the host memory and the controller without performing a write operation in the storage system memory;

receive a read command from the host that is recognized by the storage system as a write host memory command and establishes a write channel between the host memory and the controller without performing a read operation in the storage system memory;

receive data from the host for storage in the storage system memory;

prior to the data being written in the storage system memory, send, via the write channel, the data to the host for storage in the host memory; and

read, via the read channel, the data back from the host memory in response to an error in writing the data to the storage system memory.

2. The storage system of claim 1 , wherein the error is caused by a power loss.

3. The storage system of claim 1 , wherein the controller is further configured to send the data to the host for storage in a different location in the host memory than a location that initially stored the data.

4. The storage system of claim 1 , further comprising a volatile memory configured to store the data received from the host, wherein the controller is further configured to clear the data from the volatile memory prior to receiving confirmation of a successful write of the data in the storage system memory.

5. The storage system of claim 1 , wherein the storage system memory comprises a three-dimensional memory.

6. The storage system of claim 1 , wherein the controller is further configured to receive an indication from the host that the host will ignore a timeout of the write command and/or the read command.

7. The storage system of claim 1 , wherein the controller is further configured to avoid hibernation to allow the storage system to continue accessing the host memory.

8. The storage system of claim 7 , wherein the controller is further configured to avoid hibernation in response to a flag set in the storage system.

9. The storage system of claim 1 , wherein the controller is further configured to resend data to a same offset in the host memory multiple times.

10. A method comprising:

performing the following in a storage system in communication with a host, the storage system comprising a storage system memory, and the host comprising a host memory:

receiving a write command from the host that is recognized by the storage system as a read host memory command and establishes a read channel between the host memory and the controller without performing a write operation in the storage system memory;

receiving a read command from the host that is recognized by the storage system as a write host memory command and establishes a write channel between the host memory and the controller without performing a read operation in the storage system memory;

receiving data from the host for storage in the storage system memory;

prior to the data being written in the storage system memory, sending, via the write channel, the data to the host for storage in the host memory; and

reading, via the read channel, the data back from the host memory in response to an error in writing the data to the storage system memory.

11. The method of claim 10 , wherein the error is caused by a power loss.

12. The method of claim 10 , further comprising sending the data to the host for storage in a different location in the host memory than a location that initially stored the data.

13. The method of claim 10 , wherein:

the storage system comprises a volatile memory configured to store the data received from the host; and

the method further comprises clearing the data from the volatile memory prior to receiving confirmation of a successful write of the data in the storage system memory.

14. The method of claim 10 , wherein the storage system memory comprises a three-dimensional memory.

15. The method of claim 10 , further comprising receiving an indication from the host that the host will ignore a timeout of the write command.

16. The method of claim 10 , further comprising receiving an indication from the host that the host will ignore a timeout of the read command.

17. The method of claim 10 , further comprising avoiding hibernation to allow the storage system to continue accessing the host memory.

18. The method of claim 17 , further comprising avoiding hibernation in response to a flag set in the storage system.

19. The method of claim 10 , further comprising resending data to a same offset in the host memory multiple times.

20. A storage system comprising:

a storage system memory;

means for receiving a write command from a host that is recognized by the storage system as a read host memory command and establishes a read channel between the host memory and the controller without performing a write operation in the storage system memory;

means for receiving a read command from the host that is recognized by the storage system as a write host memory command and establishes a write channel between the host memory and the controller without performing a read operation in the storage system memory;

means for receiving data from the host for storage in the storage system memory;

means for sending, via the write channel, the data to the host for storage in a host memory prior to the data being written in the storage system memory; and

means for reading, via the read channel, the data back from the host memory in response to an error in writing the data to the storage system memory.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 053926 FRAME 0446 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058966/0321 →
SECURITY INTEREST Recorded Sep 29, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 053926/0446 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2020
From: SELA, ROTEM; SHAHARABANY, AMIR; KLEIN, ELIAD ADI
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052665/0497 →