IP Library Granted Patent US 12,555,955
Granted Patent B2
US 12,555,955 · App. 18/362,157 · Granted Feb 17, 2026

Vertically mountable snap fit bracket for electrolytic capacitors

Inventors: Shiqiang Sun (Shenzhen, CN); Lihwa Fong (Irvine, CA); Ning Ye (San Jose, CA)
Assignee: Sandisk Technologies, Inc.
H01R13/6273H01G2/065H01G9/02H01G9/08
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Quick Facts
Patent No.
US 12,555,955
App. No.
18/362,157
Granted
Feb 17, 2026
Kind
B2
Abstract

A snap fit bracket for an electrolytic capacitor is vertically mounted within an opening defined by a substrate. The bracket includes four sidewalls that form a perimeter. A first flange extends from one sidewall and forms a first ledge that sits on a top surface of the substrate when the bracket is mounted within the opening defined by the substrate. A second flange extends from another sidewall and forms a second ledge that sits on the top surface of the substrate when the bracket is mounted within the opening defined by the substrate. A fastener extends from two or more of the sidewalls. A top surface of each fastener contacts a bottom surface of the substrate when the bracket is mounted within the opening defined by the substrate. After vertically mounting the bracket within the substrate, the capacitor disposed within the bracket is horizontally mounted with respect to the PCB.

Claims (42)

1 . A bracket for mounting a capacitor to a substrate, comprising:

a first sidewall;

a second sidewall opposite the first sidewall;

a proximal wall extending between a proximal end of the first sidewall and a proximal end of the second sidewall;

a distal wall extending between a distal end of the first sidewall and a distal end of the second sidewall, the first sidewall, the second sidewall, the proximal wall and the distal wall defining an opening;

a first flange extending from the proximal wall and forming a first ledge that contacts a surface of the substrate when the bracket is received in an opening defined by the substrate;

a second flange extending from the distal wall and forming a second ledge that contacts the surface of the substrate when the bracket is received in the opening defined by the substrate;

a first snap fit fastener extending from the proximal wall; and

a second snap fit fastener extending from the distal wall.

2 . The bracket of claim 1 , wherein the first snap fit fastener is a v-shaped snap fit fastener.

3 . The bracket of claim 2 , wherein at least a portion of the v-shaped snap fit fastener extends below a bottom surface of the bracket.

4 . The bracket of claim 1 , wherein a top surface of the first snap fit fastener contacts a bottom surface of the substrate when the bracket is received in the opening defined by the substrate.

5 . The bracket of claim 1 , further comprising a rounded edge extending between the first sidewall and a bottom surface of the bracket.

6 . The bracket of claim 1 , further comprising an aperture defined by the proximal wall, the aperture receiving a lead of the capacitor when the capacitor is placed in the opening.

7 . The bracket of claim 1 , further comprising a first shelf provided on an inner portion of the first sidewall and a second shelf provided on an inner portion of the second sidewall, each of the first shelf and the second shelf supporting the capacitor when the capacitor is received in the opening.

8 . The bracket of claim 1 , further comprising a first ridge extending from a top surface of the first sidewall and a second ridge extending from a top surface of the second sidewall.

9 . A semiconductor package, comprising:

a substrate defining an opening;

a bracket for a capacitor provided within the opening, the bracket comprising:

a first sidewall;

a second sidewall;

a proximal wall extending between a proximal end of the first sidewall and a proximal end of the second sidewall;

a distal wall extending between a distal end of the first sidewall and a distal end of the second sidewall, the first sidewall, the second sidewall, the proximal wall and the distal wall defining a bracket opening;

a first flange extending from the proximal wall and forming a first ledge that contacts a surface of the substrate when the bracket is received in the opening defined by the substrate;

a second flange extending from the distal wall and forming a second ledge that contacts the surface of the substrate when the bracket is received in the opening defined by the substrate; and

a first snap fit fastener extending from the proximal wall; and

a second snap fit fastener extending from the distal wall.

10 . The semiconductor package of claim 9 , further comprising an electrolytic capacitor positioned within the bracket opening.

11 . The semiconductor package of claim 9 , wherein the first snap fit fastener is a v-shaped snap fit fastener.

12 . The semiconductor package of claim 9 , wherein at least a first portion of the first snap fit fastener is rounded and enables a second portion of the first snap fit fastener to move from a first position toward a second position when the second portion of the first snap fit fastener contacts an edge of the substrate within the opening defined by the substrate.

13 . The semiconductor package of claim 9 , wherein a top surface of the first snap fit fastener contacts a bottom surface of the substrate when the bracket is received in the opening defined by the substrate.

14 . The semiconductor package of claim 9 , further comprising a rounded edge extending between the first sidewall and a bottom surface of the bracket.

15 . The semiconductor package of claim 9 , further comprising an aperture defined by the proximal wall, the aperture receiving a lead of a capacitor when the capacitor is placed in the bracket opening.

16 . The semiconductor package of claim 9 , further comprising a first shelf provided on an inner portion of the first sidewall and a second shelf provided on an inner portion of the second sidewall, each of the first shelf and the second shelf supporting a capacitor when the capacitor is received in the opening.

17 . The semiconductor package of claim 9 , further comprising a first ridge extending from a top surface of the first sidewall and a second ridge extending from a top surface of the second sidewall.

18 . The semiconductor package of claim 9 , further comprising one or more pads provided on a surface of the substrate proximate to the opening.

19 . A bracket for mounting a capacitor to a substrate, comprising:

a body comprising a first sidewall, a second sidewall, a third sidewall and a fourth sidewall and defining a bracket opening;

a first support means provided on a proximal end of the body;

a second support means provided on a distal end of the body, the first support means and the second support means contacting a top surface of the substrate when the bracket is placed in an opening defined by the substrate; and

a fastening means for securing the bracket within the opening defined by the substrate, the fastening means including a surface that contacts a bottom surface of the substrate when the bracket is placed in the opening defined by the substrate.

20 . The bracket of claim 19 , further comprising a support means provided within the bracket opening, the support means supporting an electrolytic capacitor when the electrolytic capacitor is positioned within the bracket opening.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 31, 2023
From: SUN, KEN; FONG, LIHWA; YE, NING
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064438/0889 →
Continuity (2)
Provisional Application 63506708 · Jun 7, 2023
Related Publication 20240413573A1 · Dec 12, 2024
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