IP Library Granted Patent US 10,846,238
Granted Patent B2
US 10,846,238 · App. 16/455,569 · Granted Nov 24, 2020

Recovery of validity data for a data storage system

Inventors: Caesar Cheuk-Chow Cheung (Irvine, CA); Haining Liu (Irvine, CA); Subhash Balakrishna Pillai (Irvine, CA)
Assignee: Western Digital Technologies, Inc.
G06F12/1009G06F3/0604G06F3/0631G06F3/0679G06F12/0246G06F2212/1008G06F2212/1056G06F2212/202G06F2212/657G06F2212/7201G06F2212/7209
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Quick Facts
Patent No.
US 10,846,238
App. No.
16/455,569
Granted
Nov 24, 2020
Kind
B2
Abstract

The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.

Claims (53)

1. A machine-implemented method for a data storage system, comprising:

partitioning a set of logical addresses in a mapping table into a plurality of subsets of logical addresses, wherein the mapping table maps logical addresses of the set of logical addresses to respective physical addresses of a memory;

verifying each logical address in the plurality of subsets of logical addresses for a valid physical address mapped to the logical address;

for each valid physical address mapped to a logical address of the plurality of subsets of logical addresses, incrementing a validity count in a local validity table associated with a blockset of the memory corresponding to the valid physical address; and

updating validity counts in a global validity table associated with respective blocksets of the memory with the validity counts in the local validity table, wherein the global validity table is different from the local validity table, and the global validity table exists concurrently with the local validity table.

2. The machine-implemented method of claim 1 , comprising:

assigning each of the plurality of subsets of logical addresses to a respective processor core in the data storage system,

wherein a number of partitions of the logical addresses corresponds to a number of processor cores, and

wherein the machine-implemented method comprises: determining a number of available processor cores in the data storage system, wherein the number of processor cores is the number of available processor cores.

3. The machine-implemented method of claim 1 ,

wherein the mapping table is indexed by the set of logical addresses arranged sequentially, and

wherein the machine-implemented method comprises: identifying a respective starting index and a respective ending index from the set of logical addresses corresponding to a respective subset of logical addresses assigned to each processor core of the data storage system.

4. The machine-implemented method of claim 1 , wherein the memory comprises a plurality of memory devices, and wherein each of the blocksets comprises a respective physical block from a corresponding one of the plurality of memory devices.

5. The machine-implemented method of claim 4 , wherein each physical address identifies a physical data unit, and wherein each physical block comprises a plurality of physical data units.

6. The machine-implemented method of claim 1 , comprising detecting a prior abnormal shutdown of the data storage system, wherein the partitioning is performed in response to detecting the prior abnormal shutdown.

7. A data storage system comprising:

means for partitioning a set of logical addresses in a mapping table into a plurality of subsets of logical addresses, wherein the mapping table is configured to map logical addresses of the set of logical addresses to respective physical addresses of a memory;

means for verifying each logical address in the plurality of subsets of logical addresses for a valid physical address mapped to the logical address;

for each valid physical address mapped to a logical address of the plurality of subsets of logical addresses, means for incrementing a validity count in a local validity table associated with a blockset of the memory corresponding to the valid physical address; and

means for updating validity counts in a global validity table associated with respective blocksets of the memory with the validity counts in the local validity table, wherein the global validity table is different from the local validity table, and the global validity table exists concurrently with the local validity table.

8. The data storage system of claim 7 , comprising:

means for assigning each of the plurality of subsets of logical addresses to a respective processor core in the data storage system,

wherein a number of partitions of the logical addresses corresponds to a number of processor cores, and wherein the data storage system comprises: means for determining a number of available processor cores in the data storage system, wherein the number of processor cores is the number of available processor cores.

9. The data storage system of claim 7 , comprising:

means for indexing the mapping table based on the set of logical addresses arranged sequentially; and

means for identifying a respective starting index and a respective ending index from the set of logical addresses corresponding to the respective subset of logical addresses assigned to each processor core.

10. The data storage system of claim 7 , wherein the memory comprises a plurality of memory devices, and wherein each of the blocksets comprises a respective physical block from one of a plurality of memory devices.

11. The data storage system of claim 10 , wherein each physical address is configured to identify a physical data unit, and wherein each physical block comprises a plurality of physical data units.

12. The data storage system of claim 7 , comprising means for detecting a prior abnormal shutdown of the data storage system, wherein the means for partitioning is configured to perform partitioning the set of logical addresses in response to detecting the prior abnormal shutdown.

13. The data storage system of claim 7 , comprising processor cores, wherein one of the processor cores is configured to:

accumulate the validity counts from the respective local validity tables; and

update the validity counts in the global validity table associated with respective blocksets of the memory with the accumulated validity counts.

14. A data storage system, comprising:

a memory; and

a controller coupled to the memory, wherein the controller is configured to:

partition a set of logical addresses in a mapping table into a plurality of subsets of logical addresses, wherein the mapping table is configured to map logical addresses of the set of logical addresses to respective physical addresses of the memory;

check each logical address in the plurality of subsets of logical addresses for a valid physical address mapped to the logical address;

for each valid physical address mapped to a logical address of the plurality of subsets of logical addresses, increment a validity count in a local validity table associated with a blockset of the memory corresponding to the valid physical address; and

update validity counts in a global validity table associated with respective blocksets of the memory with the validity counts in the local validity table, wherein the global validity table is different from the local validity table, and the global validity table exists concurrently with the local validity table.

15. The data storage system of claim 14 , wherein the controller is configured to:

assign each of the plurality of subsets of logical addresses to a respective processor core in the data storage system,

wherein a number of partitions of the logical addresses corresponds to a number of processor cores, wherein the controller is configured to determine a number of available processor cores in the data storage system, and wherein the number of processor cores is the number of available processor cores.

16. The data storage system of claim 14 , wherein the controller is configured to:

index the mapping table using the set of logical addresses arranged sequentially; and

identify a respective starting index and a respective ending index from the set of logical addresses corresponding to the respective subset of logical addresses assigned to each processor core.

17. The data storage system of claim 14 , wherein the memory comprises a plurality of memory devices, and wherein each of the blocksets comprises a respective physical block from one of a plurality of memory devices.

18. The data storage system of claim 17 , wherein each physical address is configured to identify a physical data unit, and wherein each physical block comprises a plurality of physical data units.

19. The data storage system of claim 14 , wherein the controller is configured to:

detect a prior abnormal shutdown of the data storage system; and

partition the set of logical addresses in response to detecting the prior abnormal shutdown.

20. The data storage system of claim 14 , wherein the controller comprises processor cores, and wherein one of the processor cores is configured to:

accumulate the validity counts from the respective local validity tables; and

update the validity counts in the global validity table associated with respective blocksets of the memory with the accumulated validity counts.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
RELEASE OF SECURITY INTEREST AT REEL 052915 FRAME 0566 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 059127/0001 →
SECURITY INTEREST Recorded Feb 6, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052915/0566 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 1, 2019
From: CHEUNG, CAESAR CHEUK-CHOW; LIU, HAINING; PILLAI, SUBHASH BALAKRISHNA
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 049647/0510 →