Granted Patent B2

US 9,886,285 · App. 14/675,531 · Granted Feb 6, 2018

Abstract

Claims (53)

1. A device comprising:

a controller comprising:

a processor;

a memory interface;

an interface state machine; and

one-time programmable non-volatile storage coupled to the interface state machine, the one-time programmable non-volatile storage storing initialization parameters for training the memory interface; and

a non-volatile memory module separate from the one-time programmable non-volatile storage, the non-volatile memory module storing firmware for the device, the non-volatile memory module coupled to the controller via the memory interface;

wherein the controller is configured to:

while the processor is held in reset:

initialize the memory interface using the initialization parameters and the interface state machine; and

train the memory interface using the initialization parameters and the interface state machine;

release the processor from reset; and

execute the firmware from the non-volatile memory module using the processor and the trained memory interface.

2. The device of claim 1 , wherein the memory interface requires training before the non-volatile memory module can be accessed.

3. The device of claim 1 , wherein the memory interface is a double data rate (DDR) interface.

4. The device of claim 1 , wherein the one-time programmable non-volatile storage comprises one or more hardware registers.

5. The device of claim 4 , wherein the one or more hardware registers comprise one-time programmable hardware devices programmed during a manufacturing process.

6. The device of claim 1 further comprising one or more hardware devices configured to store bootstrap option data, wherein:

the controller is further configured to read the bootstrap option data prior to said initializing the memory interface and while the processor is held in reset; and

said initializing the memory interface is directed at least in part by the bootstrap option data.

7. The device of claim 1 , wherein the device does not include a separate boot loader ROM chip storing the firmware.

8. The device of claim 1 , wherein the device does not include a non-volatile memory chip storing the initialization parameters separate from the one-time programmable non-volatile storage.

9. The device of claim 1 , wherein the controller is further configured to boot the device without copying boot code to the non-volatile memory module.

10. The device of claim 1 , wherein the device is a data storage device.

11. The device of claim 1 , wherein the controller is further configured to perform said initializing and said training without using firmware code.

12. A method of executing firmware in a computing device, the method comprising:

while a processor of a computing device is held in reset:

accessing initialization parameters stored in one-time programmable non-volatile storage of the computing device, the initialization parameters configured for training a memory interface of the computing device;

providing the initialization parameters to an interface state machine coupled to the one-time programmable non-volatile storage via the memory interface;

initializing the memory interface using the initialization parameters and the interface state machine; and

training the memory interface using the initialization parameters and the interface state machine;

releasing the processor from reset; and

executing firmware stored in a non-volatile memory module using the processor and the trained memory interface.

13. The method of claim 12 , wherein the memory interface is a double data rate (DDR) interface.

14. The method of claim 12 , wherein the one-time programmable non-volatile storage comprises one or more hardware registers.

15. The method of claim 14 , wherein the one or more hardware registers comprise one or more fuses burned during a manufacturing process.

16. The method of claim 12 further comprising reading bootstrap option data from one or more hardware devices prior to said accessing.

17. The method of claim 12 , further comprising booting the computing device without copying boot code to the non-volatile memory module after initializing the memory interface.

18. The method of claim 12 , wherein the computing device is a data storage device.

19. The method of claim 12 , wherein said initializing and said training are performed without using firmware code.

20. A computing device comprising:

a controller comprising:

one or more processors;

a memory interface; and

one-time programmable non-volatile storage storing initialization parameters;

a non-volatile memory module separate from the one-time programmable non-volatile storage, the non-volatile memory module storing firmware for the device, the non-volatile memory module coupled to the controller via the memory interface; and

means for accessing the initialization parameters and initializing the memory interface using the initialization parameters while the one or more processors are held in reset;

wherein the controller is configured to execute the firmware from the non-volatile memory module using the one or more processors after the memory interface has been initialized.

21. The computing device of claim 20 , wherein the means for accessing the initialization parameters and initializing the memory interface comprises an interface state machine.

22. The computing device of claim 20 , wherein the memory interface is a double data rate (DDR) interface.

23. The computing device of claim 20 , wherein the controller is further configured to release the one or more processors after the memory interface has been initialized.

24. The computing device of claim 20 , wherein the one-time programmable non-volatile storage comprises one or more hardware registers.

25. The computing device of claim 24 , wherein the one or more hardware registers comprise one-time programmable hardware devices programmed during a manufacturing process.

Assignments (13)