IP Library Granted Patent US 11,513,963
Granted Patent B2
US 11,513,963 · App. 17/198,534 · Granted Nov 29, 2022

Data storage device and method for application identifier handler heads-up for faster storage response

Inventors: Ramanathan Muthiah (Bangalore, IN); Akhilesh Yadav (Bengaluru, IN)
Assignee: Western Digital Technologies. Inc.
G06F12/0875G06F12/1009G06F2212/657
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Quick Facts
Patent No.
US 11,513,963
App. No.
17/198,534
Granted
Nov 29, 2022
Kind
B2
Abstract

A data storage device and method for application identifier handler heads-up for faster storage response are provided. In one embodiment, a data storage device is provided comprising a volatile memory, a non-volatile memory, and a controller. The controller is configured to: receive data and a logical address from a host, wherein the data is tagged with an identifier of an application on the host; store the data at a physical address in the non-volatile memory; maintain a logical-to-physical address table that comprises an entry associating the logical address, physical address, and identifier; determine that the application is subsequently reloaded on the host; and cache, in the volatile memory, a portion of the logical-to-physical address table that comprises the entry for the identifier. Other embodiments are provided.

Claims (36)

1. A data storage device comprising:

a volatile memory;

a non-volatile memory; and

a controller configured to:

receive, from a host, data, an identifier of an application on the host that generated the data, and a logical address;

store the data at a physical address in the non-volatile memory;

store, in a logical-to-physical address table, an entry that maps the logical address, the physical address, and the identifier;

determine that the application is subsequently reloaded on the host by receiving from the host, the identifier of the application; and

prior to receiving, from the reloaded application, a read command with the logical address, cache, in the volatile memory, a portion of the logical-to-physical address table that comprises the entry, wherein the portion of the logical-to-physical address table is not cached in the volatile memory when the application is subsequently reloaded on the host.

2. The data storage device of claim 1 , wherein the portion of the logical-to-physical address table is cached prior to receiving, from the host, a storage command that would otherwise cause the portion of the logical-to-physical address table to be cached.

3. The data storage device of claim 1 , wherein the controller is further configured to deprioritize the portion of the logical-to-physical address table in response to receiving information from the host that the application is retired.

4. The data storage device of claim 1 , wherein the controller is further configured to make an exception to a swap-out policy for the cached portion of the logical-to-physical address table.

5. The data storage device of claim 1 , wherein the controller is further configured to store data from different applications in different logical regions of the non-volatile memory.

6. The data storage device of claim 1 , wherein the controller is further configured to store data from different applications in different non-volatile memories.

7. The data storage device of claim 1 , wherein the data storage device is configured to be integrated in the host.

8. The data storage device of claim 1 , wherein the data storage device is configured to be removably connected with the host.

9. The data storage device of claim 1 , wherein the non-volatile memory comprises a three-dimensional memory.

10. The data storage device of claim 1 , wherein the controller is further configured to observe memory access patterns of the application.

11. The data storage device of claim 10 , wherein the controller is further configured to associate logical data with the application based on the observed memory access patterns.

12. A method comprising:

performing the following in a data storage device comprising a volatile memory and a non-volatile memory:

receiving, from a host, data, an identifier of an application on the host that generated the data, and a logical address;

storing, in a logical-to-physical address table, an entry that maps the logical address, a physical address, and the identifier;

determining that the application is subsequently reloaded on the host by receiving, from the host, the identifier of the application; and

prior to receiving, from the reloaded application, a read command with the logical address, pre-loading, in the volatile memory, a portion of the logical-to-physical address table that comprises the entry, wherein the portion of the logical-to-physical address table is not cached in the volatile memory when the application is subsequently reloaded on the host.

13. The method of claim 12 , wherein the portion of the logical-to-physical address table is pre-loaded prior to receiving a storage command from the host that would otherwise cause the portion of the logical-to-physical address table to be loaded.

14. The method of claim 12 , further comprising making an exception to a swap-out policy for the pre-loaded portion of the logical-to-physical address table.

15. The method of claim 12 , further comprising storing data from different host applications in different logical regions of the non-volatile memory.

16. The method of claim 12 , further comprising storing data from different applications in different non-volatile memories in the data storage device.

17. The method of claim 12 , further comprising observing memory access patterns of the application.

18. The method of claim 17 , further comprising associating logical data with the application based on the observed memory access patterns.

19. A data storage device comprising:

a memory;

means for storing, in a logical-to-physical address table, an entry that maps a logical address, a physical address, and an identifier of an application on a host that generated data;

means for determining that the application is subsequently reloaded on the host by receiving, from the host, the identifier of the application; and

means for pre-loading a portion of the logical-to-physical address table that comprises the entry prior to receiving, from the reloaded application, a read command with the logical address, wherein the portion of the logical-to-physical address table is not cached in a volatile memory when the application is subsequently reloaded on the host.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 11, 2021
From: MUTHIAH, RAMANATHAN; YADAV, AKHILESH
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055564/0385 →