Dynamic memory controller and method for use therewith
A dynamic memory controller and method for use therewith are provided. In one example, a memory controller comprises dynamically-programmable components that can be used to configure the memory controller to be used with any number of selected host and/or memory types, as well as to enable the memory controller with different error detection/correction functionality.
1. A memory controller, comprising:
a memory interface;
a host interface; and
a processor configured to read a configuration file from a storage location external to the memory controller and to perform one or both of the following:
write values from the configuration file into a register in the memory interface to dynamically configure the memory interface to work with different types of memories; and
write values from the configuration file into a register in the host interface to dynamically configure the host interface to work with different types of hosts.
2. The memory controller of claim 1 , further comprising an error detection/correction module, wherein the processor is further configured to write values from the configuration file into a register in the error correction detection/correction module to dynamically configure the error detection/correction module with different error detection/correction functionality.
3. The memory controller of claim 1 , further comprising a clock management module, wherein the processor is further configured to write values from the configuration file into a register in the clock management module to dynamically configure the clock management module with generate different clock frequencies.
4. The memory controller of claim 1 , wherein the memory interface is dynamically configured to work with different types of memories by selecting a number of memory interface channels.
5. The memory controller of claim 1 , wherein the processor is part of an application-specific integrated circuit (ASIC), and wherein the memory interface and the host interface are not part of the ASIC.
6. The memory controller of claim 5 , wherein the ASIC further comprises one or more of the following: a multi-layer matrix (MLM) interconnect; an MLM interconnect bus interface; a peripheral, debug, and trace interface; a security and electrical fuse module; and a set of analog components.
7. The memory controller of claim 5 , further comprising a second processor that is not part of the ASIC, wherein the second processor is configured for load sharing with the processor in the ASIC.
8. In a memory controller that has a memory interface, a host interface, and a processor, a method comprising:
reading values from a memory in a storage system; and
performing one or both of the following:
programming the memory interface with the values to dynamically configure the memory interface to work with a selected one of different types of memories; and
programming the host interface with the values to dynamically configure the host interface to work with a selected one of different types of hosts.
9. The method of claim 8 , further comprising configuring an analog component in the controller with a selected clock frequency specified by the values.
10. The method of claim 8 , further comprising, prior to reading the values:
starting a boot-up process; and
programming the memory interface to be able to read the memory.
11. The method of claim 10 , further comprising, after programming the memory interface and/or host interface, loading firmware and completing the boot-up process.
12. The method of claim 8 , further comprising using a second processor in the controller for load sharing with the processor.
13. The method of claim 8 , further comprising programming an error detection/correction module with the values to enable the error detection/correction module to operate with selected parameters.
14. The method of claim 8 , wherein the processor is part of an application-specific integrated circuit (ASIC), and wherein the memory interface and the host interface are not part of the ASIC.
15. The method of claim 14 , wherein the ASIC further comprises one or more of the following: a multi-layer matrix (MLM) interconnect; an MLM interconnect bus interface; a peripheral, debug, and trace interface; a security and electrical fuse module; and a set of analog components.
16. The method of claim 8 , wherein the memory comprises a three-dimensional memory.
17. A memory controller, comprising:
an application-specific integrated circuit (ASIC);
a plurality of dynamically-programmable components located external to the ASIC; and
means for programming the dynamically-programmable components to enable to memory controller to interface with a selected memory type and/or a selected host type.
18. The memory controller of claim 17 , further comprising means for programming the dynamically-programmable components to configure the memory controller with selected error detection/correction functionality.
19. The memory controller of claim 17 , wherein the ASIC comprises one or more of the following: a processor, a multi-layer matrix (MLM) interconnect, a MLM interconnect bus interface, random access memory, a memory interface, a peripheral, debug, and trace interface, a security fuse, and an analog component.
20. The memory controller of claim 17 , wherein the plurality of dynamically-programmable components comprise one or more of the following: a host interface module, a memory interface multiplexor and channel selector, a multi-layer matrix (MLM) interconnect, a clock management module, and error correction/detection circuitry.