IP Library Granted Patent US 11,726,911
Granted Patent B2
US 11,726,911 · App. 17/185,792 · Granted Aug 15, 2023

NVMe persistent memory region quick copy

Inventors: Dudy David Avraham (Even Yehuda, IL); Ran Zamir (Ramat Gan, IL)
Assignee: Western Digital Technologies, Inc.
G06F12/0804G06F11/1004G06F2212/1032
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Quick Facts
Patent No.
US 11,726,911
App. No.
17/185,792
Granted
Aug 15, 2023
Kind
B2
Abstract

The present disclosure generally relates to data storage devices, such as solid state drives (SSDs), and efficient data storage device operations related to power loss incidents. A controller of the data storage device is configured to periodically pre-encode data that is stored in random access memory (RAM), detect a power loss event, and program the data and parity data to non-volatile memory (NVM) in response to detecting the power loss event. Upon reaching a threshold size, the data in RAM may be pre-encoded and the pre-encoded data can be programmed to the RAM or the NVM. The parity data may be stored in one or more locations of the NVM. Upon detecting a power loss event, any data remaining in RAM that is not pre-encoded is encoded. The data and any parity data not yet programmed to the NVM are programmed to the NVM.

Claims (46)

1. A data storage device, comprising:

a non-volatile memory; and

a controller coupled to the non-volatile memory, wherein the controller is configured to:

determine whether changes in random access memory (RAM) exceeds a first threshold, wherein the first threshold corresponds to a time since last pre-encoding data;

pre-encode data stored in the RAM to create parity data prior to a power loss incident, wherein the pre-encoding occurs in response to the determining;

determine that the parity data stored in the RAM is greater than a second threshold, wherein the data and the parity data is not yet programmed to the non-volatile memory, wherein the first threshold and the second threshold are distinct;

program the data associated with the parity data and the parity data stored in the RAM to the non-volatile memory when the parity data stored in the RAM is greater than the second threshold value;

detect the power loss incident; and

program only data, not yet programmed to the non-volatile memory, and only parity data, not yet programmed to the non-volatile memory, to the non-volatile memory in response to detecting the power loss incident.

2. The data storage device of claim 1 , wherein the parity data is stored in a different location in the RAM from the data.

3. The data storage device of claim 1 , wherein the programming comprises writing the data and the parity data to different locations of the non-volatile memory.

4. The data storage device of claim 1 , wherein the programming comprises jointly writing the parity data and the data to the non-volatile memory.

5. The data storage device of claim 1 , wherein the pre-encoding occurs periodically.

6. The data storage device of claim 1 , wherein the controller is further configured to monitor changes in the data in the RAM.

7. The data storage device of claim 1 , wherein the controller is further configured to check the data prior to programming the data and the parity data to the non-volatile memory.

8. The data storage device of claim 1 , wherein the pre-encoding occurs to a first section of the data prior to a second section of the data stored in the RAM.

9. The data storage device of claim 1 , wherein the programming the parity data and the data to the non-volatile memory comprises programming to single level cell (SLC) memory.

10. The data storage device of claim 1 , wherein the parity data is less than the data.

11. A data storage device, comprising:

a non-volatile memory; and

a controller coupled to the non-volatile memory, wherein the controller is configured to:

determine whether changes in random access memory (RAM) exceeds a first threshold, wherein the first threshold corresponds to a time since last pre-encoding data;

pre-encode data stored in the RAM to create parity data prior to a power loss incident, wherein the pre-encoding occurs in response to the determining;

determine that the parity data stored in the RAM is greater than a second threshold, wherein the data and the parity data is not yet programmed to the non-volatile memory, wherein the first threshold and the second threshold are distinct;

program the parity data and the data to the non-volatile memory when the parity data stored in the RAM is greater than the second threshold;

detect the power loss incident;

encode new data stored in the RAM since the programming to create new parity data in response to detecting the power loss incident; and

program the new data, not yet programmed to the non-volatile memory, and the new parity data, not yet programmed to the non-volatile memory, to the non-volatile memory.

12. The data storage device of claim 11 , wherein the parity data is programmed to a high capacity memory, and wherein the high capacity memory comprises triple level cell (TLC) memory and quad level cell (QLC) memory.

13. The data storage device of claim 12 , wherein the data, the new data, and the new parity data are programmed to SLC.

14. The data storage device of claim 11 , wherein the pre-encoding occurs to less than all available data.

15. The data storage device of claim 11 , wherein a first size of the parity data is greater than a second size of the new parity data.

16. The data storage device of claim 11 , wherein the new parity data comprises data changes since programming the parity data.

17. The data storage device of claim 11 , wherein the controller is further configured to:

determine whether changes in the RAM have exceeded the first threshold; and

upon exceeding the first threshold, pre-encode a new version of the parity data prior to the power loss incident.

18. A data storage device, comprising:

memory means;

means to determine whether changes in random access memory (RAM) exceeds a first threshold, wherein the first threshold corresponds to a time since last pre-encoding data;

means to pre-encode data to create parity data prior to detecting a power loss incident, wherein the pre-encoding occurs in response to the determining;

means to determine that the parity data stored in the RAM is greater than a second threshold, wherein the data and the parity data is not yet programmed to the memory means, wherein the first threshold and the second threshold are distinct;

means to program the data associated with the parity data and the parity data stored in the RAM to the memory means when the parity data stored in the RAM is greater than the second threshold;

means to detect a power loss incident; and

means to program only data, not yet programmed to the memory means, and only parity data, not yet programmed to the memory means, to the memory means.

19. The data storage device of claim 18 , further comprising means to selectively determine which data to pre-encode.

20. The data storage device of claim 18 , wherein the means to program is further configured to store data and parity data in different locations of the memory means.

Assignments (10)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 056285 FRAME 0292 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0001 →
SECURITY INTEREST Recorded May 19, 2021
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 056285/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 26, 2021
From: AVRAHAM, DUDY DAVID; ZAMIR, RAN
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 055431/0516 →
Continuity (2)
Provisional Application 63141211 · Jan 25, 2021
Related Publication 20220237118A1 · Jul 28, 2022