Data retention flags in solid-state drives
View Patent ↗Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.
1. A data storage device comprising:
a non-volatile memory array comprising a plurality of non-volatile memory devices; and
a controller configured to:
write data to a memory unit of the non-volatile memory array;
write a value to a memory indicating a number of bits of the written data programmed in a first of a plurality of logical states;
read the data from the non-volatile memory array;
determine a number of bits having the first of the plurality of logical states in the read data;
determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data; and
determine an effective data retention time associated with the non-volatile memory array based at least in part on the difference.
2. The data storage device of claim 1 , wherein the memory comprises at least one of: the non-volatile memory array, a volatile memory, and another non-volatile memory array.
3. The data storage device of claim 1 , wherein the first of the plurality of logical states corresponds to a value of ‘0’ and a second of the plurality of logical states corresponds to a value of ‘1.’
4. The data storage device of claim 1 , wherein the first of the plurality of logical states corresponds to a value of ‘1’ and a second of the plurality of logical states corresponds to a value of ‘0.’
5. The data storage device of claim 1 , wherein the controller is further configured to determine the effective data retention time based at least in part on a program/erase cycling condition of a portion of the non-volatile memory array.
6. The data storage device of claim 1 , wherein the controller is further configured to:
read the data from the non-volatile memory array;
determine a number of bits having the first of the logical states in the read data;
determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data; and
determine a shifted voltage read level associated with at least a portion of the non-volatile memory array based at least in part on the difference.
7. The data storage device of claim 1 , wherein the controller is further configured to write multiple copies of the value to the non-volatile memory array.
8. The data storage device of claim 7 , wherein the controller is further configured to:
write three or more copies of the value to the non-volatile memory array;
read the three or more copies of the value from the non-volatile memory array; and
determine the number of bits of the written data programmed in the first logical state by identifying two or more matching read values of the three or more copies.
9. The data storage device of claim 1 , wherein the controller is further configured to:
read the data from the non-volatile memory array;
determine a number of bits having the first of the logical states in the read data;
determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data;
determine a raw bit error rate (RBER) associated with at least a portion of the non-volatile memory array based at least in part on the difference; and
schedule a data refreshing operation for the at least a portion of the non-volatile memory array based at least in part on the RBER.
10. The data storage device of claim 1 , wherein the controller is further configured to write the data to the non-volatile memory array using a multi-level cell (MLC) programming scheme including four programming states, wherein the data is programmed to cells of the non-volatile memory array comprising an upper bit and a lower bit of information.
11. The data storage device of claim 10 , wherein the value indicates a number of cells programmed to a highest voltage state of the four programming states, wherein the controller is further configured to
read the data from the non-volatile memory array;
determine a number of read cells of the highest voltage state;
read the value from the non-volatile memory array;
determine a difference between the number of programmed cells of the highest voltage state and the number of read cells of the highest voltage state; and
determine one or more adjusted read levels associated with the non-volatile memory array based at least in part on the difference between the number of programmed cells and the number of read cells.
12. The data storage device of claim 11 , wherein the controller is further configured to determine the number of read cells of the highest voltage state at least in part by performing both upper page and lower page reads.
13. The data storage device of claim 11 , wherein the controller is further configured to write the value using cells programmed to lowest or second-lowest programming states of the four programming states.
14. The data storage device of claim 1 , wherein the controller is further configured to write the value interleaved with dummy bits to reduce cell-to-cell interference.
15. A method of managing data retention in a data storage system comprising a non-volatile memory array, the method comprising:
writing data to a memory unit of a non-volatile memory array;
writing a value to a memory indicating a number of bits of the written data programmed in a first of a plurality of logical states;
reading the data from the non-volatile memory array;
determining a number of bits having the first of the logical states in the read data;
determining a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data; and
determining an effective data retention time associated with the non-volatile memory array based at least in part on the difference;
wherein the method is performed under the control of a controller of the data storage system.
16. The method of claim 15 , wherein the memory comprises at least one of: the non-volatile memory array, a volatile memory, and another non-volatile memory array.
17. The method of claim 15 , wherein the first of the plurality of logical states corresponds to a value of ‘0’ and a second of the plurality of logical states corresponds to a value of ‘1.’
18. The method of claim 15 , wherein the first of the plurality of logical states corresponds to a value of ‘1’ and a second of the plurality of logical states corresponds to a value of ‘0.’