IP Library Granted Patent US 11,094,673
Granted Patent B2
US 11,094,673 · App. 16/692,652 · Granted Aug 17, 2021

Stacked die package with curved spacer

Inventors: Kuan-Cheng Chen (Taichung, TW); Pao-Yi Huang (Taichung, TW); Jing-Wei Hsu (Changhua, TW)
Assignee: Western Digital Technologies, Inc.
H01L25/0657H01L23/49811H01L24/45H01L25/50H01L2225/0651H01L2225/06506
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Quick Facts
Patent No.
US 11,094,673
App. No.
16/692,652
Granted
Aug 17, 2021
Kind
B2
Abstract

Apparatuses and techniques include a substrate, a controller die mounted on the substrate, fingers electrically connecting the controller die to the substrate, a spacer mounted on the substrate adjacent to the controller die, and a first memory die mounted on the spacer. The first memory die is attached to a top surface of the spacer. The spacer has a curved edge facing the controller. The curved edge may have a first curve including a first curve apex extending away from the controller, a first curve peak on one side of the first curve apex, and a second curve peak on an opposite side of the first curve apex than the first curve peak. Additional fingers connect the controller and the first memory die at a point that is aligned with the space between the first curve and a line extending from the first curve peak and the second curve peak.

Claims (45)

1. A device, comprising:

a substrate;

a controller die mounted on the substrate;

at least one finger electrically connecting the controller die to the substrate;

a spacer mounted on the substrate adjacent to the controller die; and

a first memory die mounted on the spacer,

wherein the spacer has a first curved edge facing the controller die, the first curved edge having a first curve comprising:

a first curve apex extending away from the controller die;

a first curve peak located on one side of the first curve apex; and

a second curve peak on an opposite side of the first curve apex than the first curve peak.

2. The device of claim 1 , wherein the at least one finger is in connection with the substrate at a bonding point that is vertically aligned with a space between the first curve and a line extending from the first curve peak and the second curve peak.

3. The device of claim 1 , wherein the first memory die overhangs the first curved edge of the spacer, thereby extending past the first curved edge and towards the controller die.

4. The device of claim 3 , wherein the first curve peak and the second curve peak are each closer to the controller die than the first curve apex.

5. The device of claim 3 , wherein the first curved edge further comprises a second curve comprising:

a second curve apex extending away from the controller die;

a third curve peak; and

a fourth curve peak on an opposite side of the second curve apex than the third curve peak.

6. The device of claim 5 , wherein the third curve peak and fourth curve peak are each closer to the controller die than the second curve apex.

7. The device of claim 1 , wherein the first memory die is electrically connected to the substrate with one or more bond wires.

8. The device of claim 1 , wherein the spacer comprises a second straight edge opposite the first curved edge.

9. The device of claim 8 , wherein the second straight edge is approximately flush with an edge of the first non-volatile memory die.

10. The device of claim 1 , wherein the spacer has a height that is greater than a height of the controller die.

11. The device of claim 1 , further comprising a second memory die mounted on the first memory die on a surface of the first memory die that is opposite from the spacer, at least a portion of the second memory die extending past the first memory die towards the controller die.

12. The device of claim 1 , wherein a height of the spacer is greater than a maximum height of the finger.

13. The device of claim 1 , wherein the first memory die is a NAND memory die.

14. A method of assembling a semiconductor device, comprising:

providing a substrate;

mounting a controller die on the substrate;

electrically connecting the controller die to the substrate with a plurality of first fingers;

attaching a spacer on the substrate adjacent to the controller die, the spacer comprising a first curved edge facing the controller die, the first curved edge having a first curve comprising:

a first curve apex extending away from the controller die;

a first curve peak; and

a second curve peak on an opposite side of the first curve apex than the first curve peak;

attaching a first memory die on a top surface of the spacer; and

electrically connecting the first memory die to the controller die by way of the substrate with second fingers.

15. The method of claim 14 , wherein the second fingers are electrically connected to the substrate at a bonding point that is vertically aligned with a space between the first curve and a line extending from the first curve peak and the second curve peak.

16. The method of claim 14 , wherein the first curve peak and the second curve peak are each closer to the controller die than the first curve apex.

17. The method of claim 14 , wherein the first curved edge further comprises a second curve comprising:

a second curve apex extending away from the controller die;

a third curve peak; and

a fourth curve peak on an opposite side of the second curve apex than the third curve peak.

18. The method of claim 17 , wherein the third curve peak and fourth curve peak are each closer to the controller die than the second curve apex.

19. The method of claim 14 , further comprising:

attaching a second memory die over the first memory die on a surface of the first memory die that is opposite from the spacer, at least a portion of the second memory die extending past the first memory die towards the controller die; and

electrically connecting the second memory die to the first memory die.

Assignments (8)
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 052025 FRAME 0088 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058965/0699 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 23, 2020
From: CHEN, KUAN-CHENG; HUANG, PAO-YI; HSU, JING-WEI
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 052477/0690 →
SECURITY INTEREST Recorded Feb 26, 2020
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS AGENT
Reel/Frame 052025/0088 →