Manufacturing process for separating logic and memory array
View Patent ↗A semiconductor device is disclosed including an integrated memory module. The integrated memory module may include a pair of semiconductor die, which together, operate as a single, integrated flash memory. In one example, the first die may include the memory cell array and the second die may include the logic circuit such as CMOS integrated circuits. In one example, the second die may be flip-chip bonded to the first die. The flip-chip bond pads on the first and second dies may be made small, with a small pitch, to allow a large number of electrical interconnections between the first and second semiconductor dies.
1. An integrated memory module comprising:
a first semiconductor die comprising a first group of bond pads and a second group of bond pads;
a second semiconductor comprising a third group of bond pads flip-chip bonded to the first group of bond pads of the first semiconductor die to electrically and physically couple the second semiconductor die to the first semiconductor die;
wherein the first and second coupled semiconductor dies together are configured as an integrated flash memory.
2. The integrated memory module of claim 1 , wherein the first semiconductor die comprises a plurality of memory cells.
3. The integrated memory module of claim 2 , wherein the second semiconductor die comprises a control circuit for controlling access to the plurality of memory cells.
4. The integrated memory module of claim 3 , wherein the control circuit comprises a complementary metal-oxide-semiconductor integrated circuit.
5. The integrated memory module of claim 1 , wherein the second group of bond pads on the first semiconductor die are configured to receive electrical connectors for electrically connecting the integrated memory module to a host device.
6. The integrated memory module of claim 1 , wherein the second group of bond pads on the first semiconductor die are configured to receive wire bonds for electrically connecting the integrated memory module to a host device.
7. An integrated memory module comprising:
a first semiconductor die comprising:
a plurality of memory cells,
a first group of bond pads electrically coupled to the plurality of memory cells, and
a second group of bond pads;
a second semiconductor comprising:
control circuits for controlling access to the plurality of memory cells on the first semiconductor die, and
a third group of bond pads flip-chip bonded the first group of bond pads of the first semiconductor die to electrically and physically couple the second semiconductor die to the first semiconductor die;
wherein the first and second coupled semiconductor dies together are configured as an integrated flash memory.
8. The integrated memory module of claim 7 , wherein the number of bond pads in the third group coupled to the bond pads in the first group comprise between 100 and 1,000.
9. The integrated memory module of claim 7 , wherein the number of bond pads in the third group coupled to the bond pads in the first group comprise between 10,000 and 100,000.
10. The integrated memory module of claim 7 , wherein the control circuits comprises a complementary metal-oxide-semiconductor integrated circuit.
11. The integrated memory module of claim 7 , wherein the second group of bond pads on the first semiconductor die are configured to receive electrical connectors for electrically connecting the integrated memory module to a host device.
12. The integrated memory module of claim 1 , wherein the second group of bond pads on the first semiconductor die are configured to receive wire bonds for electrically connecting the integrated memory module to a host device.
13. A method of fabricating a semiconductor device, comprising:
(a) forming a first plurality of bond pads on a first semiconductor die;
(b) forming a second plurality of bond pads on a second semiconductor die; and
(c) mounting at least some of the first plurality of bond pads to the second plurality of bond pads, the first semiconductor die and the second semiconductor die together being configured as an integrated flash memory.
14. The method of claim 13 , wherein said step (c) of mounting at least some of the first plurality of bond pads to the second plurality of bond pads comprises mounting the at least some of the first plurality of bond pads to the second plurality of bond pads after the first semiconductor die and the second semiconductor die have been diced from a wafer.
15. The method of claim 13 , wherein said step (c) of mounting at least some of the first plurality of bond pads to the second plurality of bond pads comprises mounting the at least some of the first plurality of bond pads to the second plurality of bond pads after the first semiconductor die has been severed from a wafer and before the second semiconductor die has been severed from the wafer.
16. The method of claim 13 , wherein said step (c) of mounting at least some of the first plurality of bond pads to the second plurality of bond pads comprises mounting the at least some of the first plurality of bond pads to the second plurality of bond pads before the first semiconductor die has been severed from a wafer and before the second semiconductor die has been severed from a wafer.
17. The method of claim 13 , wherein said step (c) of mounting at least some of the first plurality of bond pads to the second plurality of bond pads comprises applying solder to a pair of bond pads to be connected to each other and melting the solder using thermo-compression.
18. The method of claim 17 , wherein said step (c) of mounting at least some of the first plurality of bond pads to the second plurality of bond pads comprises applying solder to a pair of bond pads to be connected to each other and melting the solder using ultrasonic bonding.
19. The method of claim 13 , wherein said step (c) of mounting at least some of the first plurality of bond pads to the second plurality of bond pads comprises applying a micro-bump to one bond pad of a pair of bond pads to be connected to each other, and melting the micro-bump using thermo-compression.
20. The method of claim 13 , wherein said step (c) of mounting at least some of the first plurality of bond pads to the second plurality of bond pads comprises a Cu-to-Cu bonding bringing the pair of bond pads together under pressure.
21. An integrated memory module comprising:
a first semiconductor die comprising first bond pad means for electrically connecting the first semiconductor die, and second bond pad means for electrically connecting the first semiconductor die;
a second semiconductor comprising third bond pads means for flip-chip bonding to the first bond pad means;
wherein the first and second coupled semiconductor dies together are configured as an integrated flash memory.