Automatic bit line voltage and bit line voltage temperature compensation adjustment for non-volatile memory apparatus current consumption reduction
A memory apparatus and method of operation are provided. The apparatus includes memory cells disposed in memory holes connected to bit lines. The memory cells are configured to retain a threshold voltage corresponding to data states. The memory holes are grouped into a plurality of blocks. A control means is coupled to the bit lines and is configured to determine an amount of the memory cells of one of the plurality blocks that are programmed. The control means adjusts a bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed. The control means applies the adjusted bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of read levels associated with the data states in a read operation.
1 . A memory apparatus, comprising:
memory cells disposed in memory holes each connected to one of a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory holes grouped into a plurality of blocks; and
a control means coupled to the plurality of bit lines and configured to:
determine an amount of the memory cells of one of the plurality blocks that are programmed,
adjust a bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed, and
apply the adjusted bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of a plurality of read levels associated with each of the plurality of data states in a read operation.
2 . The memory apparatus as set forth in claim 1 , wherein the memory cells are each connected to one of a plurality of word lines, and the control means is further configured to:
read the memory cells connected to a predetermined set of the plurality of word lines to determine whether the memory cells connected thereto are programmed before the read operation, the predetermined set of the plurality of word lines selected to correspond with specific amounts of the memory cells being programmed;
determine the amount of the memory cells of one of the plurality blocks that are programmed based on reading the memory cells connected to the predetermined set of the plurality of word lines;
apply the adjusted bit line voltage to the plurality of bit lines; and
read the memory cells to determine whether the memory cells have the threshold voltage above one or more of the plurality of read levels associated with each of the plurality of data states in the read operation.
3 . The memory apparatus as set forth in claim 2 , further including predetermined values for the bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed at each of the specific amounts of the memory cells being programmed and the control means is further configured to select and use the predetermined values for the bit line voltage based on a comparison of the amount of the memory cells of the one of the plurality blocks that are programmed compared to the specific amounts of the memory cells being programmed.
4 . The memory apparatus as set forth in claim 1 , further including a power circuit configured to measure an electrical current consumed by the memory apparatus, and the control means is further configured to:
using the power circuit, sense a peak magnitude of the electrical current consumed by the memory apparatus during the read operation;
determine the amount of the memory cells of the one of the plurality blocks that are programmed based on the peak magnitude of the electrical current consumed by the memory apparatus during the read operation;
adjust the bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed and apply the adjusted bit line voltage to the plurality of bit lines; and
continue reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of the plurality of read levels associated with each of the plurality of data states in the read operation.
5 . The memory apparatus as set forth in claim 4 , wherein the control means is further configured to:
determine whether the peak magnitude of the electrical current consumed by the memory apparatus during the read operation exceeds a predetermined threshold peak magnitude; and
consider the amount of the memory cells of the one of the plurality blocks that are programmed to be approximately zero in response to the peak magnitude of the electrical current consumed by the memory apparatus during the read operation exceeding the predetermined threshold peak magnitude.
6 . The memory apparatus as set forth in claim 1 , wherein the memory cells are each connected to one of a plurality of word lines, the memory apparatus further includes block openness data stored and updated in the memory apparatus and configured to track which of the plurality of word lines were last programmed in each of the plurality of blocks, and the control means is further configured to:
determine the amount of the memory cells of one of the plurality blocks that are programmed based on the block openness data before the read operation;
adjust the bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed and apply the adjusted bit line voltage to the plurality of bit lines; and
read the memory cells to determine whether the memory cells have the threshold voltage above one or more of the plurality of read levels associated with each of the plurality of data states in the read operation.
7 . The memory apparatus as set forth in claim 1 , further including a temperature detection circuit configured to measure a temperature of the memory apparatus, wherein the bit line voltage is modified by a bit line voltage temperature compensation coefficient, and the control means is further configured to:
determine the temperature of the memory apparatus; and
adjust and utilize the bit line voltage temperature compensation coefficient based on the temperature of the memory apparatus.
8 . A controller in communication with a memory apparatus including memory cells disposed in memory holes each connected to one of a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory holes are grouped into a plurality of blocks, the controller configured to:
determine an amount of the memory cells of one of the plurality blocks that are programmed;
instruct the memory apparatus to adjust a bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed; and
instruct the memory apparatus to apply the adjusted bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of a plurality of read levels associated with each of the plurality of data states in a read operation.
9 . The controller as set forth in claim 8 , wherein the memory cells are each connected to one of a plurality of word lines, and the controller is further configured to:
instruct the memory apparatus to read the memory cells connected to a predetermined set of the plurality of word lines to determine whether the memory cells connected thereto are programmed before the read operation, the predetermined set of the plurality of word lines selected to correspond with specific amounts of the memory cells being programmed;
determine the amount of the memory cells of one of the plurality blocks that are programmed based on reading the memory cells connected to the predetermined set of the plurality of word lines;
instruct the memory apparatus to apply the adjusted bit line voltage to the plurality of bit lines; and
instruct the memory apparatus to read the memory cells to determine whether the memory cells have the threshold voltage above one or more of the plurality of read levels associated with each of the plurality of data states in the read operation.
10 . The controller as set forth in claim 9 , wherein the memory apparatus further includes predetermined values for the bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed at each of the specific amounts of the memory cells being programmed and the controller is further configured to select and use the predetermined values for the bit line voltage based on a comparison of the amount of the memory cells of the one of the plurality blocks that are programmed compared to the specific amounts of the memory cells being programmed.
11 . The controller as set forth in claim 8 , wherein the memory apparatus further includes a power circuit configured to measure an electrical current consumed by the memory apparatus, and the controller is further configured to:
instruct the memory apparatus to sense a peak magnitude of the electrical current consumed by the memory apparatus during the read operation using the power circuit;
determine the amount of the memory cells of the one of the plurality blocks that are programmed based on the peak magnitude of the electrical current consumed by the memory apparatus during the read operation;
instruct the memory apparatus to adjust the bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed and apply the adjusted bit line voltage to the plurality of bit lines; and
instruct the memory apparatus to continue reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of the plurality of read levels associated with each of the plurality of data states in the read operation.
12 . The controller as set forth in claim 11 , wherein the controller is further configured to:
determine whether the peak magnitude of the electrical current consumed by the memory apparatus during the read operation exceeds a predetermined threshold peak magnitude; and
consider the amount of the memory cells of the one of the plurality blocks that are programmed to be approximately zero in response to the peak magnitude of the electrical current consumed by the memory apparatus during the read operation exceeding the predetermined threshold peak magnitude.
13 . The controller as set forth in claim 8 , wherein the memory cells are each connected to one of a plurality of word lines, the memory apparatus further includes block openness data stored and updated therein and configured to track which of the plurality of word lines were last programmed in each of the plurality of blocks, and the controller is further configured to:
determine the amount of the memory cells of one of the plurality blocks that are programmed based on the block openness data before the read operation;
instruct the memory apparatus to adjust the bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed and apply the adjusted bit line voltage to the plurality of bit lines; and
instruct the memory apparatus to read the memory cells to determine whether the memory cells have the threshold voltage above one or more of the plurality of read levels associated with each of the plurality of data states in the read operation.
14 . A method of operating a memory apparatus including memory cells disposed in memory holes each connected to one of a plurality of bit lines, the memory cells configured to retain a threshold voltage corresponding to one of a plurality of data states, the memory holes grouped into a plurality of blocks, the method comprising the steps of:
determining an amount of the memory cells of one of the plurality blocks that are programmed;
adjusting a bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed; and
applying the adjusted bit line voltage to the plurality of bit lines while reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of a plurality of read levels associated with each of the plurality of data states in a read operation.
15 . The method as set forth in claim 14 , wherein the memory cells are each connected to one of a plurality of word lines, and the method further includes the steps of:
reading the memory cells connected to a predetermined set of the plurality of word lines to determine whether the memory cells connected thereto are programmed before the read operation, the predetermined set of the plurality of word lines selected to correspond with specific amounts of the memory cells being programmed;
determining the amount of the memory cells of one of the plurality blocks that are programmed based on reading the memory cells connected to the predetermined set of the plurality of word lines;
applying the adjusted bit line voltage to the plurality of bit lines; and
reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of the plurality of read levels associated with each of the plurality of data states in the read operation.
16 . The method as set forth in claim 15 , wherein the memory apparatus further includes predetermined values for the bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed at each of the specific amounts of the memory cells being programmed and the method further includes the step of selecting and using the predetermined values for the bit line voltage based on a comparison of the amount of the memory cells of the one of the plurality blocks that are programmed compared to the specific amounts of the memory cells being programmed.
17 . The method as set forth in claim 14 , wherein the memory apparatus further includes a power circuit configured to measure an electrical current consumed by the memory apparatus, and the method further includes the steps of:
using the power circuit, sensing a peak magnitude of the electrical current consumed by the memory apparatus during the read operation;
determining the amount of the memory cells of the one of the plurality blocks that are programmed based on the peak magnitude of the electrical current consumed by the memory apparatus during the read operation;
adjusting the bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed and apply the adjusted bit line voltage to the plurality of bit lines; and
continuing reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of the plurality of read levels associated with each of the plurality of data states in the read operation.
18 . The method as set forth in claim 17 , wherein further including the steps of:
determining whether the peak magnitude of the electrical current consumed by the memory apparatus during the read operation exceeds a predetermined threshold peak magnitude; and
considering the amount of the memory cells of the one of the plurality blocks that are programmed to be approximately zero in response to the peak magnitude of the electrical current consumed by the memory apparatus during the read operation exceeding the predetermined threshold peak magnitude.
19 . The method as set forth in claim 14 , wherein the memory cells are each connected to one of a plurality of word lines, the memory apparatus further includes block openness data stored and updated therein and configured to track which of the plurality of word lines were last programmed in each of the plurality of blocks, and the method further includes the steps of:
determining the amount of the memory cells of one of the plurality blocks that are programmed based on the block openness data before the read operation;
adjusting the bit line voltage based on the amount of the memory cells of the one of the plurality blocks that are programmed and apply the adjusted bit line voltage to the plurality of bit lines; and
reading the memory cells to determine whether the memory cells have the threshold voltage above one or more of the plurality of read levels associated with each of the plurality of data states in the read operation.
20 . The method as set forth in claim 14 , wherein the memory apparatus further includes a temperature detection circuit configured to measure a temperature of the memory apparatus, the bit line voltage is modified by a bit line voltage temperature compensation coefficient, and the method further includes the steps of:
determining the temperature of the memory apparatus; and
adjusting and utilizing the bit line voltage temperature compensation coefficient based on the temperature of the memory apparatus.