IP Library › Granted Patent US 10,741,257
Granted Patent B1
US 10,741,257 · App. 16/453,291 · Granted Aug 11, 2020

Dynamic bit line voltage and sensing time enhanced read for data recovery

Inventors: Jianzhi Wu (San Jose, CA); Xiang Yang (San Jose, CA)
Assignee: SanDisk Technologies LLC
G11C16/26G11C16/24G11C16/3404
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Quick Facts
Patent No.
US 10,741,257
App. No.
16/453,291
Granted
Aug 11, 2020
Kind
B1
Abstract

A method and system are provided for reading a non-transitory memory array. When a default read operation is performed and has failed, a dynamic sensing bit line voltage (VBLC) enhanced read or a dynamic sense time read is performed. According to the dynamic VBLC enhanced read or the dynamic sense time enhanced read, the VBLC or the sense time is increased, and a read is performed with the increased VBLC or increased sense time. If this enhanced read is unsuccessful, and if a maximum VBLC or a maximum sense time has not yet been reached, the VBLC or the sense time is increased again, and another read is performed. Once the maximum VBLC or a maximum sense time has been reached, if the read is still not successful, a read failure is reported.

Claims (51)

1. A method of reading a non-transitory memory array, the method comprising:

performing a default read of a memory array by applying a default sensing bit line voltage (VBLC) and using a default sense time;

upon determining that the default read is unsuccessful, performing one of a dynamic VBLC enhanced read of the memory array and a dynamic sense time enhanced read of the memory array,

wherein the dynamic VBLC enhanced read comprises:

(a) increasing the VBLC, such that VBLC i =VBLC (i-1) +ΔVBLC, where i is a non-zero integer,

(b) performing a read of the memory array using the increased VBLC i ;

(c) if the read not successful, determining if the VBLC i has reached a voltage maximum;

(d) if the VBLC i has reached the voltage maximum, reporting a read failure;

(e) if the VBLC i has not reached the voltage maximum, repeating operations (a)-(e); and

wherein the dynamic sense time enhanced read comprises:

(a′) increasing the sense time t, such that t i =t (i-1) +Δt, where i is a non-zero integer,

(b′) performing a read of the memory array using the increased sense time t;

(c′) if the read not successful, determining if the sense time t i has reached a time maximum;

(d′) if the sense time t i has reached the time maximum, reporting a read failure;

(e′) if the sense time t i has not reached the voltage maximum, repeating operations (a′)-(e′).

2. The method according to claim 1 , wherein ΔVBLC is 50 mV and Δt is 200 ns.

3. The method according to claim 1 , wherein the voltage maximum is 300 mV, and the time maximum is 1200 ns.

4. A non-volatile memory storage system comprising:

a memory cell array comprising a plurality of blocks of memory cells; and

a dynamic enhanced read circuit configured to perform a default read of the memory cell array by applying a default sensing bit line voltage (VBLC) and using a default sense time, and upon determining that the default read is unsuccessful, perform one of a dynamic VBLC enhanced read of the memory cell array and a dynamic sense time enhanced read of the memory cell array,

wherein the dynamic VBLC enhanced read comprises:

(a) increasing the VBLC, such that VBLC i =VBLC (i-1) +ΔVBLC, where i is a non-zero integer,

(b) performing a read of the memory array using the increased VBLC i ;

(c) if the read not successful, determining if the VBLC i has reached a voltage maximum;

(d) if the VBLC i has reached the voltage maximum, reporting a read failure;

(e) if the VBLC i has not reached the voltage maximum, repeating operations (a)-(e); and

wherein the dynamic sense time enhanced read comprises:

(a′) increasing the sense time t, such that t i =t (i-1) +Δt, where i is a non-zero integer,

(b′) performing a read of the memory array using the increased sense time t;

(c′) if the read not successful, determining if the sense time t i has reached a time maximum;

(d′) if the sense time t i has reached the time maximum, reporting a read failure;

(e′) if the sense time t i has not reached the voltage maximum, repeating operations (a′)-(e′).

5. The system according to claim 4 , wherein ΔVBLC is 50 mV and Δt is 200 ns.

6. The system according to claim 4 , wherein the voltage maximum is 300 mV, and the time maximum is 1200 ns.

7. A non-volatile computer-readable medium having recorded thereon a program which, when executed by a processor, causes the processor to execute a method comprising:

performing a default read of a memory array by applying a default sensing bit line voltage (VBLC) and using a default sense time;

upon determining that the default read is unsuccessful, performing one of a dynamic VBLC enhanced read of the memory array and a dynamic sense time enhanced read of the memory array,

wherein the dynamic VBLC enhanced read comprises:

(a) increasing the VBLC, such that VBLC i =VBLC (i-1) +ΔVBLC, where i is a non-zero integer,

(b) performing a read of the memory array using the increased VBLC i ;

(c) if the read not successful, determining if the VBLC i has reached a voltage maximum;

(d) if the VBLC i has reached the voltage maximum, reporting a read failure;

(e) if the VBLC i has not reached the voltage maximum, repeating operations (a)-(e); and

wherein the dynamic sense time enhanced read comprises:

(a′) increasing the sense time t, such that t i =t (i-1) +Δt, where i is a non-zero integer,

(b′) performing a read of the memory array using the increased sense time t i ;

(c′) if the read not successful, determining if the sense time t i has reached a time maximum;

(d′) if the sense time t i has reached the time maximum, reporting a read failure;

(e′) if the sense time t i has not reached the voltage maximum, repeating operations (a′)-(e′).

8. The non-volatile computer-readable medium according to claim 7 , wherein ΔVBLC is 50 mV and Δt is 200 ns.

9. The non-volatile computer-readable medium according to claim 7 , wherein the voltage maximum is 300 mV, and the time maximum is 1200 ns.

Assignments (4)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 30, 2019
From: WU, JIANZHI; YANG, XIANG
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 049906/0345 →
Cited By (1)
US 12,524,177