IP Library Granted Patent US 11,853,603
Granted Patent B2
US 11,853,603 · App. 17/454,880 · Granted Dec 26, 2023

Host memory buffer cache management

Inventors: Judah Gamliel Hahn (Ofra, IL); Shay Benisty (Beer Sheva, IL); Ariel Navon (Revava, IL)
Assignee: Western Digital Technologies, Inc.
G06F3/0659G06F3/0604G06F3/0656G06F3/0679
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Quick Facts
Patent No.
US 11,853,603
App. No.
17/454,880
Granted
Dec 26, 2023
Kind
B2
Abstract

The present disclosure generally relates to host memory buffer (HMB) cache management. HMB is transient memory and may not always be available. For example, when the link between the data storage device and the host device is not active, the data storage device can't access the HMB. Placing an HMB log in the HMB controller that is disposed in the data storage device provides access to data that would otherwise be inaccessible in the HMB. The HMB log contains any deltas that have occurred since either the last copying to an HMB cache in the memory device or any delta that have occurred since the link became inactive. The HMB cache mirrors the HMB. In so doing, the data of the HMB is available to the data storage device not only when the link is active, but also when the link is not active.

Claims (39)

1. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

determine whether a link is active between a host memory buffer (HMB) and the controller;

write data into a cache, wherein the data written into the cache is data intended to be written in the HMB, wherein the data is delta data; and

update a HMB log to indicate a presence of delta data.

2. The data storage device of claim 1 , wherein the controller is further configured to update HMB with the delta data once the link is active and wherein the controller is further configured to mirror data in the HMB by writing data to an HMB cache disposed in the memory device.

3. The data storage device of claim 1 , wherein the determining determines that the link is not active, wherein upon updating the HMB log, data in the HMB is different from data stored in an HMB cache.

4. The data storage device of claim 3 , wherein the data in HMB is identical to a combination of data stored in HMB cache and the delta data.

5. A data storage device, comprising:

a memory device; and

a controller coupled to the memory device, wherein the controller is configured to:

receive a request to write data to a host memory buffer (HMB);

log an indication of the write to a HMB log;

write the data into a cache, wherein the data is delta data;

receive a read request to read data from HMB;

retrieve a portion of requested data from a location other than HMB;

retrieve the delta data; and

return the delta data and the portion of requested data to fulfil the read request.

6. The data storage device of claim 5 , wherein the controller is further configured to determine that a link between the controller and the HMB is not active.

7. The data storage device of claim 6 , wherein the link is not active when the portion of requested data and the delta data are retrieved.

8. The data storage device of claim 5 , wherein the cache is disposed in the controller.

9. The data storage device of claim 5 , wherein the portion of requested data is retrieved from an HMB cache.

10. The data storage device of claim 9 , wherein the HMB cache is disposed in the memory device.

11. The data storage device of claim 5 , wherein the controller is further configured to write the delta data to HMB upon determining that a link between the HMB and the controller is active.

12. The data storage device of claim 5 , wherein the controller is configured to write the delta data to HMB prior to receiving the read request.

13. The data storage device of claim 5 , wherein the controller is configured to determine whether the HMB log is full.

14. The data storage device of claim 5 , wherein the controller is configured to consolidate data from the HMB log and flush the consolidated data to the memory device.

15. A data storage device, comprising:

memory means; and

a controller coupled to the memory means, wherein the controller is configured to:

receive requests to read data from and write data to a host memory buffer (HMB);

process the read requests by retrieving requested data from a location other than the HMB; and

process the write requests by writing data to a location other than the HMB, wherein the data is written to HMB after writing the data to the location other than the HMB.

16. The data storage device of claim 15 , wherein the data associated with the read request is disposed in HMB, the memory means, and a SRAM cache.

17. The data storage device of claim 15 , wherein the controller further comprises a management engine, wherein the management engine comprises an HMB log and SRAM cache.

18. The data storage device of claim 15 , wherein the location other than the HMB comprises a cache disposed in the controller.

19. The data storage device of claim 15 , wherein the controller is further configured to log writing of data to the location other than the HMB.

20. The data storage device of claim 15 , wherein the controller is further configured to copy data from the location other than the HMB to the HMB upon determining that a link between the HMB and the controller is active.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 15, 2021
From: HAHN, JUDAH GAMLIEL; BENISTY, SHAY; NAVON, ARIEL
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058117/0197 →