IP Library Granted Patent US 12,248,395
Granted Patent B2
US 12,248,395 · App. 18/226,385 · Granted Mar 11, 2025

Data storage device and method for predictable low-latency in a time-sensitive environment

Inventors: Devika Nair (Bangalore, IN); Amit Sharma (Bangalore, IN)
Assignee: Sandisk Technologies, Inc.
G06F12/0215G06F11/08G06F2212/1024
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Quick Facts
Patent No.
US 12,248,395
App. No.
18/226,385
Granted
Mar 11, 2025
Kind
B2
Abstract

A data storage device and method are provided for predictable low-latency in a time-sensitive environment. In one embodiment, a data storage device is provided comprising a memory and a controller configured to communicate with the memory. The controller is further configured to: receive, from a host, an indication of a logical block address range that the host will later read; and in response to receiving the indication: read data from the logical block address range; and perform an action on the data to reduce a read latency when the host later reads the logical block address range. Other embodiments are disclosed.

Claims (40)

1. A data storage device comprising:

a non-volatile memory array;

a data cache; and

a processor configured to communicate with the memory and further configured to:

receive, from a host, an indication of a logical block address range that the host will later read;

in response to receiving the indication:

read original data from the non-volatile memory array, wherein the original data is stored in the non-volatile memory array with a set of parity bits; and

store a copy of the data in the non-volatile memory array with fewer, if any, parity bits than what is stored with the original data in the non-volatile memory array;

receive a command from the host to read the logical block; and

in response to receiving the command from the host to read the logical block address range, read, from the non-volatile memory array, the copy of the data instead of the original data, wherein because the copy of the data is stored in the non-volatile memory array with fewer, if any, parity bits than what is stored in the non-volatile memory array with the original data, reading the copy of the data from the non-volatile memory array instead of reading the original data from the non-volatile memory array reduces read latency because fewer parity bits are read from the non-volatile memory array.

2. The data storage device of claim 1 , wherein the data is time-sensitive data.

3. The data storage device of claim 1 , wherein the copy of the data is stored in a single-level cell (SLC) memory in the non-volatile memory array.

4. The data storage device of claim 1 , wherein the copy of the data is stored in an area of the non-volatile memory array reserved for time-sensitive data.

5. The data storage device of claim 1 , wherein the host comprises an automated vehicle.

6. The data storage device of claim 1 , wherein the host comprises a robot.

7. The data storage device of claim 1 , wherein the memory comprises a three-dimensional memory.

8. A method comprising:

performing in a data storage device comprising a non-volatile memory array and a data cache:

receiving, from a host, an indication of a logical block address range that the host will later read;

in response to receiving the indication:

reading original data from the non-volatile memory array, wherein the original data is stored in the non-volatile memory array with a set of parity bits; and

storing a copy of the data in the non-volatile memory array with fewer, if any, parity bits than what is stored with the original data in the non-volatile memory array;

receiving a command from the host to read the logical block; and

in response to receiving the command from the host to read the logical block address range, reading, from the non-volatile memory array, the copy of the data instead of the original data, wherein because the copy of the data is stored in the non-volatile memory array with fewer, if any, parity bits than what is stored in the non-volatile memory array with the original data, reading the copy of the data from the non-volatile memory array instead of reading the original data from the non-volatile memory array reduces read latency because fewer parity bits are read from the non-volatile memory array.

9. The method of claim 8 , wherein the data is time-sensitive data.

10. The method of claim 8 , wherein the copy of the data is stored in a single-level cell (SLC) memory in the non-volatile memory array.

11. The method of claim 8 , wherein the copy of the data is stored in an area of the non-volatile memory array reserved for time-sensitive data.

12. The method of claim 8 , wherein the host comprises an automated vehicle.

13. The method of claim 8 , wherein the host comprises a robot.

14. The method of claim 8 , wherein the non-volatile memory array comprises a three-dimensional memory.

15. A data storage device comprising:

a non-volatile memory array;

a data cache; and

means for:

receiving, from a host, an indication of a logical block address range that the host will later read;

in response to receiving the indication:

reading original data from the non-volatile memory array, wherein the original data is stored in the non-volatile memory array with a set of parity bits; and

storing a copy of the data in the non-volatile memory array with fewer, if any, parity bits than what is stored with the original data in the non-volatile memory array;

receiving a command from the host to read the logical block; and

in response to receiving the command from the host to read the logical block address range, reading, from the non-volatile memory array, the copy of the data instead of the original data, wherein because the copy of the data is stored in the non-volatile memory array with fewer, if any, parity bits than what is stored in the non-volatile memory array with the original data, reading the copy of the data from the non-volatile memory array instead of reading the original data from the non-volatile memory array reduces read latency because fewer parity bits are read from the non-volatile memory array.

Assignments (8)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PATENT COLLATERAL AGREEMENT Recorded Aug 23, 2024
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS THE AGENT
Reel/Frame 068762/0494 →
CHANGE OF NAME Recorded Jun 27, 2024
From: SANDISK TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067982/0032 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2024
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 067567/0682 →
PATENT COLLATERAL AGREEMENT - DDTL Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065657/0158 →
PATENT COLLATERAL AGREEMENT- A&R Recorded Nov 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 065656/0649 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2023
From: NAIR, DEVIKA; SHARMA, AMIT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 064390/0600 →
Continuity (2)
Provisional Application 63471411 · Jun 6, 2023
Related Publication 20240411678A1 · Dec 12, 2024
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