Memory controller implemented error correction code memory

1. An apparatus comprising:

a memory controller configured to:

select, as an error correction code (ECC) group, a first diagonal stripe of bit groups across banks of a dynamic random access memory (DRAM), the DRAM comprising multiple banks;

select, as a user data group, a second diagonal stripe of bit groups across the banks of the DRAM;

receive a write command for the DRAM;

determine ECC data associated with the write command;

write user data from the write command to memory cells in the user data group; and

write the ECC data to memory cells in the ECC group; and

a physical channel coupled to the memory controller and configured for communication with the DRAM.

2. The apparatus of claim 1 , wherein the first diagonal stripe of bit groups in the ECC group has a single bit group in each bank of the DRAM.

3. The apparatus of claim 2 , wherein, to select the first diagonal stripe of bit groups across banks of the DRAM, the memory controller is configured to:

select a first bit group at a first row offset within a first bank of the DRAM; and

increment the first row offset with each successive bank after the first bank for a next bit group in the ECC group, the first row offset determined by a modulus operation on banks in the memory.

4. The apparatus of claim 3 , wherein the incrementing is implemented by an exclusive-OR of three most significant address bits for the DRAM with three least significant row address bits.

5. The apparatus of claim 3 , wherein the ECC data has a row offset in a bank and the user data has the row offset in a different bank.

6. The apparatus of claim 1 , wherein the stripe of bit groups reside on a single DRAM integrated circuit (IC).

7. The apparatus of claim 1 , wherein the stripe of bit groups reside on multiple DRAM integrated circuits (ICs).

8. The apparatus of claim 1 , wherein the ECC group is one eighth of a row width or two-hundred and fifty-six bytes.

9. A method comprising:

selecting, by a memory controller, a first diagonal stripe of bit groups across banks of a dynamic random access memory (DRAM) as error correction code (ECC) group, the DRAM comprising multiple banks;

selecting, as a user data group, a second diagonal stripe of bit groups across the banks of the DRAM;

receiving a write command for the DRAM;

determining ECC data associated with the write command;

writing user data from the write command to memory cells in the user data group; and

writing, using a physical channel coupled to the memory controller and the DRAM, ECC data to memory cells in the ECC group.

10. The method of claim 9 , wherein the first diagonal stripe of bit groups in the ECC group has a single bit group in each bank of the DRAM.

11. The method of claim 10 , wherein selecting the first diagonal stripe of bit groups across banks of the DRAM includes:

selecting a first bit group at a first row offset within a first bank of the DRAM; and

incrementing the first row offset with each successive bank after the first bank for a next bit group in the ECC group, the first row offset determined by a modulus operation on banks in the memory.

12. The method of claim 11 , wherein the incrementing is implemented by exclusive-ORing three most significant address bits for the DRAM with three least significant row address bits.

13. The method of claim 11 , wherein the ECC data has a row offset in the bank and the user data has the row offset in a different bank.

14. The method of claim 9 , wherein the stripe of bit groups reside on a single DRAM integrated circuit (IC).

15. The method of claim 9 , wherein the stripe of bit groups reside on multiple DRAM integrated circuits (ICs).

16. The method of claim 9 , wherein the ECC group is one eighth of a row width or two-hundred and fifty-six bytes.

17. A non-transitory machine-readable medium including instructions that, when executed, cause circuitry of a memory controller to perform operations comprising:

selecting a first diagonal stripe of bit groups across banks of a dynamic random access memory (DRAM) as error correction code (ECC) group, the DRAM comprising multiple banks;

selecting, as a user data group, a second diagonal stripe of bit groups across the banks of the DRAM;

receiving a write command for the DRAM;

determining ECC data associated with the write command;

writing user data from the write command to memory cells in the user data group; and

writing, using a physical channel coupled to the memory controller and the DRAM, ECC data to memory cells in the ECC group.

18. The non-transitory machine-readable medium of claim 17 , wherein the first diagonal stripe of bit groups in the ECC group has a single bit group in each bank of the DRAM.

19. The non-transitory machine-readable medium of claim 18 , wherein selecting the first diagonal stripe of bit groups across banks of the DRAM includes:

selecting a first bit group at a first row offset within a first bank of the DRAM; and

incrementing the first row offset with each successive bank after the first bank for a next bit group in the ECC group, the first row offset determined by a modulus operation on banks in the memory.

20. The non-transitory machine-readable medium of claim 19 , wherein the incrementing is implemented by exclusive-ORing three most significant address bits for the DRAM with three least significant row address bits.

21. The non-transitory machine-readable medium of claim 19 , wherein the ECC data has a row offset in the bank and the user data has the row offset in a different bank.

22. The non-transitory machine-readable medium of claim 17 , wherein the stripe of bit groups reside on a single DRAM integrated circuit (IC).

23. The non-transitory machine-readable medium of claim 17 , wherein the stripe of bit groups reside on multiple DRAM integrated circuits (ICs).

24. The non-transitory machine-readable medium of claim 17 , wherein the ECC group is one eighth of a row width or two-hundred and fifty-six bytes.